EDBT 2026 Demo / reviewers in the wild / expert
Gerd Neuendorf
dblp:69/5426
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1990
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 44% Electronic design automation · 44% Energy-efficient computing · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 1 | 1990 | Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1990 | Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990 |
Energy-efficient computing
dynamic power dissipation |
0.0 | 1 | 1990 | Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990 |
Methods — techniques the papers use, named apart from their topics
multi-objective optimization · 0.0analytical delay modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1990 | Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipationabstractSignal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits.> Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |