Testing of one-dimensional (1-D) unilateral iterative logic arrays (ILA's) of combinational cells with constant test vectors is studied and the concept of one repetition length (ORL) within the tests used for testing C-testable arrays is described. The impact of ORL on the test set size and the design of the test generator are discussed. ORL can dramatically reduce the on-chip test generator size with a negligible increase in the test set size. ORL, coupled with a single distinguishing sequence (DS) for ILA's with cell vertical outputs has proved to be attractive in terms of both reduced test set size and reduced test generator size. ORL testability can be used for C-testable arrays with single faulty cell and multiple faulty cells. The technique for using a single linear finite state machine (LFSM) for generating the necessary deterministic test patterns followed optionally by pseudorandom patterns from the same automaton is discussed. Use of an LFSM as a built-in test generator for only deterministic tests for 1-D ILA's is covered. With ORL, a compact LFSM based built-in self test (BIST) generator can deliver the test vectors to all the cells in the array. The exact probability distribution equation has been developed for additional bits needed to map a nonlinear machine (FSM) definition into a LFSM definition. The distribution clearly shows that the expected number of additional bits is very small, often zero.>

A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One application of this method is illustrated where deterministic at-speed testing of C-testable ILAs, covering all possible single and multiple combinational faults is achieved. Response analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of BIST hardware are explained.>