Multilevel flash memories store more than one bit per storage cell and are further characterized by large word (page) sizes and very low target error rates. In this paper, a high-rate error control scheme is presented that uses inner trellis-coded modulation (TCM) for storing two bits per cell with five possible charge levels. The coded subset-label bits and the uncoded signal-label bits of TCM are independently protected by separate outer Reed-Solomon (RS) codes. The resulting scheme permits multistage decoding. Errors made by the TCM decoder in the subset-label bits occur in bursts and are corrected by the associated first RS decoder prior to determining signal-label bits and correcting errors in those bits by the associated second RS decoder. The multi-stage decoding avoids the significant spread of errors from subset-label bits into the generally larger number of signal-label bits which is typical for conventional serial RS-TCM concatenation when the inner TCM system operates at relatively low SNR. The error performance of the proposed scheme is evaluated at low error rates by a mixed simulation-analytic method. It is shown that the proposed scheme exhibits highly favorable performance vs. complexity tradeoffs compared to the other schemes.

Shannon's determination of the capacity of the linear Gaussian channel has posed a magnificent challenge to succeeding generations of researchers. This paper surveys how this challenge has been met during the past half century. Orthogonal minimum-bandwidth modulation techniques and channel capacity are discussed. Binary coding techniques for low-signal-to-noise ratio (SNR) channels and nonbinary coding techniques for high-SNR channels are reviewed. Recent developments, which now allow capacity to be approached on any linear Gaussian channel, are surveyed. These new capacity-approaching techniques include turbo coding and decoding, multilevel coding, and combined coding/precoding for intersymbol-interference channels.

100BASE-T2 is a new physical layer specification for IEEE 802.3 LANs operating at 100 Mbit/s ("fast Ethernet"). It enables users of the 10BASE-T Ethernet LAN technology to upgrade their networks from 10 Mbit/s to 100 Mbit/s performance while retaining an existing voice-grade cabling infrastructure. 100BASE-T2 transceivers will operate over two pairs in unshielded twisted-pair cables corresponding to EIA/TIA category 3 (UTP-3), which is the minimum requirement for 10BASE-T. In a four-pair UTP-3 cable, simultaneous operation of two 100BASE-T2 links, or one 100BASE-T2 and one 10BASE-T link, is permitted. Since voice-grade cables exhibit more signal attenuation and significantly higher crosstalk coupling between adjacent pairs than data-grade cables, sophisticated digital signal processing techniques are needed to achieve reliable 100 Mbit/s transmission. The 100BASE-T2 standard defines dual-duplex baseband transmission at a modulation rate of 25 MBaud. During each modulation interval, a four-bit data nibble or Ethernet specific control information is encoded into a pair of quinary signals. These signals are transmitted simultaneously on the two wire pairs in both signalling directions. In the receivers, adaptive digital filters are required for echo and NEXT cancellation, equalization, and interference suppression.

This paper deals with multilevel partial-response class-IV (PRIV) transmission over unshielded twisted-pair (UTP) cables. Specifically, transmission at a rate of 155.52 Mb/s over data-grade UTP cables for local-area networking is considered. As a low-complexity method used to compensate for cable-length dependent signal distortion, adaptive analog equalization with two controlled parameters is proposed: one parameter determines a frequency-independent receiver gain, the other parameter controls the transfer characteristic of a variable analog receive-filter section. For the stepwise design of the transmit and receive filters, a combination of analytic techniques and simulated annealing is employed. First, the variable equalizer section, then the remaining fixed analog receive filter section are developed and finally the analog transmit filter is determined. The paper also describes the adjustment of the equalizer section, and the control of the sampling phase in the receiver front-end. The two equalizer parameters are controlled by an algorithm that operates on the sampled signals and adjusts these parameters to optimum settings independently of the sampling phase. The latter is controlled by a decision-directed phase-locked loop algorithm that becomes effective when equalization has been achieved. The dynamic behaviour and mean-square error in steady-state obtained with these control algorithms are investigated.

The paper describes an experimental transceiver for full-duplex transmission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (QPRIV) overall-channel signaling with near-end crosstalk (NEXT) cancellation and maximum-likelihood sequence detection is employed. The spectral shape of the QPRIV signals facilitates equalization and achieving compliance with EMC regulations. Since in an FDDI system each transmitter can be clocked independently, the receiver must cope with phase drift between NEXT signals to be cancelled and signals received from the remote transmitter. With the chosen transceiver architecture, digital-to-analog conversion of transmit signals, analog-to-digital conversion of receive signals, and adaptive NEXT cancellation are performed synchronously with the transmitter clock. The rate change from transmit timing to controlled receive timing is accomplished by an adaptive equalizer in conjunction with an elastic buffer and occasional coefficient shifts. The equalizer is adjusted rapidly enough to allow for a maximal phase drift of ±100 ppm. The implementation of all digital signal-processing functions in a single 0.5 μm CMOS VLSI prototype chip is discussed. The employed standard-cell design resulted in a power consumption of 6 W. Significantly lower power consumption can be achieved by custom design of highly repetitive processing elements

The paper describes the decoding of unconstrained L-ary signals (L/spl ges/2) transmitted over a noisy partial-response channel with transfer function 1-D/sup 2/. Signals received at even and odd sampling times are independently decoded in a pipeline fashion. After stating the known results for full-state maximum-likelihood sequence decoding, a 2-state decoding algorithm is introduced in which the difference between the metrics of the retained two most-likely states is iteratively computed. An analysis of its error-event probability shows that two types of error events are most likely, regular free-distance events and induced free-distance events. The latter cause only a rather small degradation of error performance compared to full-state decoding. In addition, the symbol-error probability for modulo-L encoded user symbols and decoding with finite decoding delay is computed. The 2-state decoder can be realized for arbitrary values of L with low hardware complexity.>

A general parity-check equation is presented that defines rotationally invariant trellis codes of rate k/(k+1) for two-dimensional signal sets. This parity-check equation is used to find rate k/(k+1) codes for 4PSK, 8PSK, 16PSK, and QAM signal sets by systematic code searches. The MPSK codes exhibit smaller free Euclidean distances than nonrotationally invariant linear codes with the same number of states. However, since the nonlinear codes have a smaller number of nearest neighbors, their performance at moderate signal to noise ratios is close to that of the best linear codes. The rotationally invariant QAM codes with 8, 32, 64, and 256 states achieve the same free Euclidean distance as the best linear codes. Transparency of user information under phase rotations is accomplished either by conventional differential encoding and decoding, or by integrating this function directly into the code trellis.>

A 2L-dimensional multiple phase-shift keyed (L*MPSK) signal set is obtained by forming the Cartesian product of L two-dimensional MPSK signal sets. A systematic approach to partitioning L*MPSK signal sets that is based on block coding is used. An encoder system approach is developed. It incorporates the design of a differential precoder, a systematic convolutional encoder, and a signal set mapper. Trellis-coded L*4PSK, L*8PSK, and L*16PSK modulation schemes are found for 1>

Fast initial training of a voiceband data-modem receiver which employs an equalizer with fractionl-Tspaced coefficients is presented. The modem receiver performs rapid gain acquisition, and monitors the equalizer delay line for the presence of a periodic training signal whose period is equal to the length of the equalizer delay line. Testing for periodicity is combined with estimating carrier-frequency offset. Once a full period of the training signal has been obtained, the equalizer coefficients are computed by spectral division, and coefficient centering is performed. The receiver then proceeds in a reference-directed mode until the end of the training signal is detected. In the paper, algorithms for rapid gain acquisition and the detection of a cyclic training signal in the presence of noise and carrier-frequency offset are presented. Cyclic training of an equalizer with fractional-Tspaced coefficients is derived. It is shown that the equalizer coefficients can be computed efficiently by spectral division. Coefficient centering, carrier-phase and symbol synchronization, reference-directed training, and the transition to data mode are described. Finally, measurement results for an experimental 2400 baud modem using an equalizer with 64T/2-spaced coefficients are given. The modem achieves a startup time of 20 ms on a Bell 3002 unconditioned leased line.

We consider trellis-coding techniques for improving the reliability of digital transmission over noisy partial-response channels. Such channels are commonly encountered in digital communication systems, and also play a role in devices for data recording. Concentrating on the channels with characteristics(1 \mp D), we study methods to obtain codes which increase free Euclidean distance between permitted sequences of channel outputs and avoid the occurrence of unlimited runs of identical outputs at the expense of some loss in data rate. One technique employs the concept of set partitioning. The other is based on using convolutional codes designed for maximum free Hamming distance in conjunction with a precoder. Both methods lead to essentially equivalent codes.

The SP16 processor executes typical signal-processing tasks efficiently by overlapping in each processor cycle four functions: instruction prefetching, data-memory access and transfer of one data word over a single data bus, ALU operation, and multiplication. Despite SP16 being a one-address machine with a single data bus, it can perform filter operations with a multiplication and ALU operation in every processor cycle.

The paper deals with the design of digital transmitter and receiver filters with finite impulse response (FIR) for data transmission over band-limited channels. The filters are matched and satisfy a zero intersymbol interference constraint when cascaded. For baseband transmission, the filters achieve optimum spectral concentration in the frequency range[-(1+\beta)/2T, (1+\beta)/2T]. Mathematically, the filter design leads to a generalized eigenvalue problem which is solved numerically by a projected gradient Procedure. For transmission over bandpass channels by combined amplitude and phase modulation, the design technique is modified so that filters with complex-valued impulse response and optimum spectral concentration in the range of positive bandpass frequencies[f_{c} - (1+\beta)/2T, f_{c} + (1+\beta)/2T]are obtained. In addition, the complex formulation allows the design of impulse responses with enhanced spectral attenuation in the corresponding range of negative frequencies in order to minimize imageband interference. Results are shown in terms of filter coefficients, signal spectra, and spectral concentrations obtained. For example, filters designed for a voiceband data modem operating at a symbol rate of 2400 baud achieve a spectral concentration of 98.5 percent with 24 coefficients and\beta = 0.1, and with only 0.001 percent of the total energy in the imageband region.

A coding technique is described which improves error performance of synchronous data links without sacrificing data rate or requiring more bandwidth. This is achieved by channel coding with expanded sets of multilevel/phase signals in a manner which increases free Euclidean distance. Soft maximum--likelihood (ML) decoding using the Viterbi algorithm is assumed. Following a discussion of channel capacity, simple hand-designed trellis codes are presented for 8 phase-shift keying (PSK) and 16 quadrature amplitude-shift keying (QASK) modulation. These simple codes achieve coding gains in the order of 3-4 dB. It is then shown that the codes can be interpreted as binary convolutional codes with a mapping of coded bits into channel signals, which we call "mapping by set partitioning." Based on a new distance measure between binary code sequences which efficiently lower-bounds the Euclidean distance between the corresponding channel signal sequences, a search procedure for more powerful codes is developed. Codes with coding gains up to 6 dB are obtained for a variety of multilevel/phase modulation schemes. Simulation results are presented and an example of carrier-phase tracking is discussed.

Adaptive equalizers are usually realized in the form of a transversal filter with variable tap gains and tap spacing equal to the symbol spacingT. The performance of these equalizers depends critically on the symbol-clock phase derived in the receiver, due to the clock-phase dependent aliasing of the spectral roll-off components, upon which the conventional equalizer has no influence. In this paper we study the possibility of overcoming this difficulty by making the tap spacing of the equalizer somewhat smaller thanT(fractional tap spacing). It is shown that this leads to satisfactory performance of the equalizer for a broad continuous range of clock phases, without penalizing the speed of convergence. Furthermore, it allows the application of a simple clock recovery scheme which derives a phase control signal from the equalizer tap-gain values.

A new look is taken at maximum-likelihood sequence estimation in the presence of intersymbol interference. A uniform receiver structure for linear carrier-modulated data-transmission systems is derived which for decision making uses a modified version of the Viterbi algorithm. The algorithm operates directly on the output signal of a complex matched filter and, in contrast to the original algorithm, requires no squaring operations; only multiplications by discrete pulse-amplitude values are needed. Decoding of redundantly coded sequences is included in the consideration. The reason and limits for the superior error performance of the receiver over a conventional receiver employing zero-forcing equalization and symbol-by-symbol decision making are explained. An adjustment algorithm for jointly approximating the matched filter by a transversal filter, estimating intersymbol interference present at the transversal filter output, and controlling the demodulating carrier phase and the sample timing, is presented.