Field Programmable Gate Arrays (FPGAs) used in mission-critical applications such as aerospace, nuclear, and defense require high reliability in spite of internal faults. Fortunately, today's FPGAs have the ability to dynamically reconfigure themselves in the field, which may help to mitigate the effects of certain faults affecting the FPGA devices. Although the reconfiguration process can remove only the upsets affecting the configuration bitstream, unfortunately, there are other sources of faults that might directly affect hardware resources of reconfigurable FPGAs. Their nature and consequences differ from those which occur in the configuration bitstream and their effects cannot be corrected by performing configuration writeback. This paper proposes a fault-aware configurable logic block architecture to detect such faults in FPGA-implemented logic circuits. The fault coverage of the proposed architecture is also discussed. Hardware complexity estimations suggest higher efficiency of the approach proposed over similar existing ones.

Several approaches to design of fault-secure or/and fault-tolerant digital finite input response (FIR) filters with varying fault coverage and hardware efficiency have been proposed. However, no specific implementations in modern nanometric technologies using error detecting codes like residue codes or parity codes has been reported yet. In this paper, we will study design of fault-secure multipliers-accumulators (MACs) and digital FIR filters protected using residue codes. Several versions of the fault-secure transpose digital FIR filters were synthesized using RC Compiler v.8.1 for the 65 nm technology. The results obtained leave no doubts that residue codes could be extremely efficient, because hardware overhead for the transpose digital FIR filters with 16-bit operands, protected using residue code mode 3, is below 2%, which is significantly less than by using any other technique reported to date. To note that, unlike claimed in some recent works, should some elementary design rules be applied, the circuits proposed can guarantee the 100% error coverage.

In this paper, we propose a polymorphic fault tolerant architecture that can be tailored to efficiently support the reliability needs of multiple applications at run-time. Today, coarse-grained reconfigurable architectures (CGRAs) host multiple applications with potentially different reliability needs. Providing platform-wide worst-case (maximum) protection to all the applications is neither optimal nor desirable. To reduce the fault-tolerance overhead, adaptive fault-tolerance strategies have been proposed. The proposed techniques access the reliability requirements of each application and adjust the fault-tolerance intensity (and hence overhead), accordingly. However, existing flexible reliability schemes only allow to shift between different levels of modular redundancy (duplication, triplication, etc.) and deal with only a single class of faults (e.g. soft errors). To complement these strategies, we propose energy-aware fault-tolerance that, in addition to modular redundancy, can also provide low cost, sub-modular (e.g. residue mod 3) redundancy, to cater both permanent and temporary faults. Our solution relies on an agent based control layer and a configurable fault-tolerance data path. The control layer identifies the application class and configures the data path to provide the needed reliability. Simulation results using a few selected algorithms (FFT, matrix multiplication, and FIR filter) showed that the proposed method provides flexible protection with energy overhead ranging from 3.125% to 107% for different reliability levels. Synthesis results have confirmed that the proposed architecture significantly reduces the area overhead for self-checking (59.1%) and fault tolerant (7.1%) versions, compared to the state of the art adaptive reliability techniques.

In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time). The efficiency of the proposed approach was validated through fault injection experiments.

In this paper, we present a new residue number system (RNS) {2n-1, 2n, 2n+1, 2n+1+1, 2n-1+1} of five well-balanced moduli that are co-prime for odd n. This new RNS complements the 5-moduli RNS system proposed before for even n {2n-1, 2n, 2n+1, 2n+1-1, 2n-1-1}. With the new set, we also present a novel approach to designing multi-moduli reverse converters that focuses strongly on critical path analysis and aims at strongly on moving a significant amount of computations off the critical path. The synthesis of the resulting design over the ST Microelectronics 65nm LP library demonstrates that the delay, area, and power characteristics improve the performance and power consumption of the existing complementary 5-moduli set.

This paper presents the implementation of the error recovery scheme from temporary faults, applicable for datapaths of coarse-grained reconfigurable architectures. We have chosen the DART architecture as a vehicle to study various aspects related to implementation of the instruction retry in a complex highly parallel reconfigurable system. Synthesis results have confirmed the time, hardware, and power consumption efficiency of the proposed approach, which can be applied independently on the concurrent error detection scheme actually used.

The generation of the remainder of the integer division by one or more moduli is essential in various applications involving residue number system (RNS), arithmetic error control coding, and cryptography. In this paper, we consider the possibility of designing multi-residue generators capable of sharing hardware which, unlike previous designs, are not limited to the pairs of conjugate moduli 2a− 1 and 2a−1+ 1only. We show that logic circuitry can be shared by residue generators modulo any moduli whose period or half-period parameters have common divisors and are at least three times larger than the number of inputs of the generators. For some subsets of moduli, over 40% hardware reduction is observed.

Berger-invert codes are coding schemes used to protect communication channels against all asymmetric errors and to decrease power consumption. This paper proposes a method of constructing modified Berger-invert codes that relies on the choice of check parts with the smallest possible total weight and assignment of low-weight check parts to the most numerous subsets of data with the largest Hamming weights. As a result, the error rate of the transmitted data can be reduced by up to about 23.5% for a 8-bit bus at no cost (no extra bus lines or increase of hardware to implement encoding and decoding/checking circuitry).

In this paper, we propose a new design method for modulo 2a-1 multipliers which accept double representation of 0 of input operands. The new multiplier takes advantage of the symmetric properties of integers written in l's complement representation which allows to reduce the size of carry-save adders (CSAs) used. Currently, for small a they are the least complex (in terms of the number of logic gates) multipliers modulo 2a-1 available in the open literature.

2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propagation. Residue Number System (RNS) breaks free of these bonds by decomposing a number into parts and performing arithmetic operations in parallel, significantly reducing the breadth of carry propagation. Consequently, RNS arithmetic has been proposed as a solution to improve the power-efficiency of arithmetic hardware. However, limitations of the expressiveness of RNS in terms of arithmetic operations together with overheads related to interaction with 2's complement arithmetic make programmable processor design that takes advantage of these benefits challenging.

The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting codes is considered. The main idea relies on using the RAM check bits to control the correct operation of the parallel cyclic code encoder, so that the whole interface has no single point of failure.

Like other silicon integrated circuit (IC) domains, the smart card market is very competitive and main actors are constantly trying to design the cheapest and safest circuits to ensure their consumers' satisfaction. These specificities lead smart cards actors to design standard cell-based tamper resistant ICs and to characterize their circuits1 sensitivity. In this paper, we present some experimental results aimed at characterizing the sensitivity to laser-induced transient pulses (and their duration) of elementary cells from the 0.13 mum standard cell library STM HCM0S9GP. They were obtained for a specially designed and fabricated experimental circuit. The data obtained here allow us for better understanding of laser attacks and would be used to design integrated circuits with better protection against such attacks. The final goal of this work is to build and augment new simulation models dedicated to laser-induced faults aimed specifically at smart card industry

Several techniques for extracting data from smart cards have been described in the literature, including the so called differential fault analysis (DFA) that relies on perturbing the chip operations to deduce the data. In this paper, we present some experimental results of the DFA that relies on using a laser beam.

We consider the open problem of designing fault-secure parallel encoders for various systematic linear ECC. The main idea relies on generating not only the check bits for error correction but also, separately and in parallel, the check bits for error detection. Then, the latter are compared against error detecting check bits which are regenerated from the error correcting check bits. The detailed design is presented for encoders for CRC codes. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that their fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation. Future research will include the design of FS decoders for CRC codes as well as the generalization of the presented ideas to design of FS encoders and decoders for other systematic linear ECC like nonbinary BCH codes and Reed-Solomon codes.

This paper tackles the open problem of designing combinational self-testing checkers (STCs) for K-pair 2-rail codes which are self-testing, even by a subset of codewords, such that some input lines are 0 (or 1) for only one input codeword. The checker presented in the paper has both theoretical and practical importance. It is useful, for example, to build STCs for other systematic error-detecting codes, like Berger codes with I = 2/sup K-1/ data bits and arithmetic codes with the check base A = 2/sup K-1/+I (K = 3, 4, 5, ...). It also allows the designers to build functional totally self-checking circuits with 100% fault coverage in which such 2-rail codes could not have been used otherwise.

For original paper see ibid., vol.42, no.8, p.1020-4 (1994). T.R.N. Rao et al. (1994) proposed a totally self-checking (TSC) 2-output checker for Berger codes with I=2/sup r-1/ information bits. The article shows that their checker may not be self-testing, as claimed. Hence, the circuit proposed by S.J. Piestrak (2002) is the first correct solution of this design problem.

The optimal codes C(n,t) capable of detecting t-unidirectional errors in an n-bit vector were defined by Borden (1982). Unidirectional errors have been observed in modern digital devices such as PLAs, ROMs, and compact laser disks. In this paper, a new approach to designing self-testing checkers (STCs) for Borden codes is proposed. The new STC is built of a self-testing code-disjoint translator of the Borden code into the 1-out-of-z code (z/spl ges/2) and if z=3 or 4 an STC for the 1-out-of-n code. The translator is built of two multi-output threshold circuits with [n/2] and [n/2] inputs and a merging network. Compared to existing STCs for Borden codes the new checker generally uses significantly less hardware. It also enjoys a modular and highly regular structure which makes it attractive for VLSI implementation.

This paper presents the design of minimal-level PLA self-testing checkers (STCs) for incomplete m-out-of-n (m/n) codes and 1-out-of-n (1/n) codes. All checkers are selftesting for three classes of typical PLA faults and hence they are all crosspoint irredundant. A number of various incomplete m/n codes which exhibit the two-closure property with balanced partitioning are constructed, which allow one to build two-level area optimal PLA STCs for incomplete m/n codes with virtually any capacity. These new PLA STC's for m/n codes are then used to build a family of efficient three-level PLA STCs for most 1/n codes. In most cases, the new checkers offer area and/or active device number reduction, compared to existing designs which rely upon m/2m codes only. Obviously, all new minimal-level checkers can be implemented using logic gates as well.

This paper considers design of totally self-checking (TSC) code-disjoint (CD) PLA's under fault model which covers three classes of typical PLA faults. The inputs of a PLA are encoded with a separable unordered code and any PLA is inverter-free, which guarantees that it is crosspoint-irredundant and no bridging fault may cause undetected errors. The new optimal separable unordered codes are constructed which, unlike most Berger and equivalent codes, are closed-a prerequisite for a TSC/CD realization of a PLA. A general procedure for designing a fast 2-stage PLA self-testing checker for any optimal separable unordered closed code is given. The design approach presented here can be readily used to design non-PLA circuits as well.>

The carry-free nature of the residue number system (RNS) has made it attractive for implementing a variety of specialized high-performance digital signal processing systems. A new implementation of a high-speed residue-to-binary converter based on the Chinese Remainder Theorem (CRT) is proposed. It employs a new r-operand adder modulo M, realized using carry-save adders and its delay path involves only one addition of two a-bit operands performed by some carry-propagate adder, where M is the dynamic range and a=[log/sub 2/ M]. The latter feature is in contrast with any other CRT-based converter that has been proposed to date, which require two subsequent additions of a-bit operands. This circuit offers a latency period significantly smaller than the fastest known designs.>

Residue generator is an essential building block of encoding/decoding circuitry for arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In either case, a residue generator is an overhead for a system and as such it should be built with minimum amount of hardware and should not compromise the speed of a system. Multioperand modular adder (MOMA) is a computational element used to implement various operations in digital signal processing systems using RNS. A comprehensive study of new residue generators and MOMA's is presented. The design methods given here take advantage of the periodicity of the series of powers of 2 taken module A (A is a module). Four design schemes of the n-input residue generators mod A, which are best suited for various pairs of n and A, are proposed. Their pipelined versions can be clocked with the cycle determined by the delay of a full-adder and a latch. A family of design methods for parallel and word-serial, using similar concepts, is also given. Both classes of circuits employ new highly-parallel schemes using carry-save adders with end-around carry and a minimal amount of ROM and are well-suited for VLSI implementation. They are faster and use less hardware than similar circuits known to date. One of the MOMA's can be used to build a high-speed residue-to-binary converter based on the Chinese remainder theorem.>

It is shown that an n-input sorting network (SN) can be used to implement an n-variable symmetric threshold functions using the least amount of hardware. An algorithm to derive Boolean functions implemented on any line of any n-input threshold circuit T/sup n/ implemented as a SN is given. A heuristic procedure for generating the minimal test set for any threshold circuit T/sup n/ implemented as a Batcher's SN or any other SN is presented. The number of tests required to detect all stuck-at faults in an n-input SN is determined. A highly regular structure using only one type of simple cell and a suitability for low-level pipelining are other advantages of the circuit T/sup n/. The circuit T/sup n/ can be used as a basic building block of various circuitry supporting the use of all known unidirectional error detecting codes.>

The design of residue generators and multioperand modular adders is studied. Novel highly parallel schemes using carry-save adders with end-around carry are proposed for either type of circuit. They are derived on the basis of the periodicity of the series of powers of two taken modulo A (A is a module). The novel circuits are faster and use less hardware than existing similar circuits.>

A Borden code is an optimal code capable of detecting t-unidirectional errors. A new self-testing checker (STC) for Borden code is proposed. It is built of two blocks: a self-testing code-disjoint translator of the Borden code onto the one-out-of-r code (r>or=4) and a well-known STC for the one-out-of-r code. The translator is built of two multi-output threshold circuits and a NOT-AND-OR circuit. The new checker has significantly better performance than the STC for Borden code proposed previously by N. K. Jha (1989). Its highly regular modular structure and easy testability make it particularly attractive for a VLSI implementation.>

Methods for designing self-testing checkers (STCs) for arithmetic error-detecting codes are presented. First, general rules for the design of minimal-level STCs for any error-detecting code are given. The design is illustrated with STCs for 3N+B codes, 0>

The Berger codes are optimal separable codes that detect all undirectional errors. In this correspondence a new procedure of designing self-testing checkers (STC's) for codes with I information bits, where I = {2K-2, 2K-l} and I ≥ 3, is proposed. I ≥ 3. The new checker is basically composed of u = ⌈(I + 1)/2⌉ STC's for m-out-of-n codes with n = I + 1 and m = 2p + 1, O ≤ p ≤ u -1. Simple STC for the codes with I = 2K-1is also given. All new checkers can be implemented as inverter-free circuits and hence be self-testing for all unidirectional faults. Comparison to earlier designs reveals essential improvement in speed of operation.