The multiplexing of several lightly loaded links onto a more heavily loaded output link is a problem of considerable importance to the design and traffic engineering of many types of packet-oriented telecommunications equipment, including that used in Asynchronous Transfer Mode (ATM) networks. Network configurations generally require the cascaded operation of such multiplexers and switches. Important objectives to achieve small cell loss ratios while maintaining efficient utilization of the transmission links. The small cell loss ratio objective results in extremely long simulation runs. To address this problem, we propose a new technique that relies on a compact description for the arriving/departing traffic at the multiplexers and a time-parallel scheme without fix-up phases for effective parallelization. The technique does not make assumptions about the analytical nature of the arrival process, thereby allowing trace-driven simulations to be performed as well. We demonstrate the method for a number of configurations and traffic scenarios, and observe that it yields one to two orders of magnitude speedup on a 32 processor Kendall Square Research KSR-1 multiprocessor compared to an efficient cell-level simulation executing on a Sparc-10 workstation.

In a telecommunications network, the use of time division switches which directly operate on Pulse Code Modulated bit streams requires the use of some means for synchronizing the clock rates of such switches. Various methods for achieving synchronization are discussed. Master-slave synchronization has been selected as the most appropriate approach for the Bell System's switched digital network. Some aspects of this approach are considered.