This paper presents a DC-DC Buck converter featuring an adaptive constant on-time (ACOT) control technique, designed to maintain high efficiency across a wide load range for Internet of Things (IoT) applications. The converter utilizes a voltage feedback loop to maintain a stable 3.3V output voltage and ensure fast transient response. Additionally, a current-sensor-based feedback loop detects load changes to maintain system stability and efficiency. The ACOT control block dynamically adjusts between modes to optimize efficiency under varying load conditions. Implemented in 0.18 μm BCD technology, the proposed converter occupies 0.63 mm2of silicon area. Operating with a nominal 5V input, it supports an output load current range of 10 μA to 2A, maintaining efficiencies above 90% and achieving a peak efficiency of 97% at a 500kHz switching frequency. With automatic mode transitions, output ripple remains below 20mV under a 5V input, ensuring performance stability across operating conditions.

This article presents a 26–32-GHz 6-bit bidirectional passive vector modulation phase shifter (PVM-PS) in 40-nm CMOS for phased array systems. The passive phase shifter comprises a center-tap transformer-based quadrature generator/combiner, two 6-bit X-type attenuators, and a differential Wilkinson power combiner/divider. The symmetric design enables bidirectional signal propagation and offers flexible system configuration. Passive switches are sized to optimize the tradeoff among gain variation, insertion loss, and linearity. The phase shifter implemented in 40 nm covers a range of 360° with 5.625° resolution and the rms phase error is between 0.4° and 1.3°. It exhibits <1-dB magnitude imbalance and <1.2° phase imbalance between forward and reverse propagation modes. Its OP1dB is above −1 dBm across the operation frequency.

This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies$220\times 630\,\,\mu \text{m}^{2}$and has no power consumption.

This paper presents a monolithically integrated E-band amplifier multiplier chain (AMC) developed in 130 nm SiGe BiCMOS process. This E-band AMC is composed of a 25 GHz 1:1 power divider, two 25 GHz driver amplifiers (DA1,2), a 75 GHz passive frequency tripler, and a 75 GHz power amplifier (PA). By applying a bypass tuning capacitor based power enhancing technique in the single-ended DA and PA, the output power and power-added-efficiency (PAE) of the AMC have been effectively improved. Benefiting from the proposed passive tripler core with second harmonic suppression function, and the impedance matching network with frequency selection characteristics, the AMC presents better harmonic suppression performance compared with the conventional topology. The bias circuits with temperature compensation are applied to the DA and PA to ensure the performance of the AMC when the temperature changes. The AMC has a measured output power exceeding 0 dBm in the entire E-band frequency range with a peak output power of 10.9 dBm at 77 GHz, and exhibits a record PAE of 8.25 %. Within the 3 dB operating frequency range from 69 to 87 GHz, the rejection of fundamental and second harmonics are better than 33.5 dB. The AMC can work properly between −40°C and 125 °C with the proposed temperature compensation bias circuits.

Wideband beamforming is widely required in the sub-6GHz frequency band for 5G commutation and the next generation wireless communication (B5G). The true time delay is the most crucial component, especially in the sub-6GHz frequency band. This paper presents a new true time delay by using an N-path switch capacitor delay cell to break the tradeoff between bandwidth and delay range by introducing tunable sampling clocks. The non-idealities and limitations are discussed as well. In a 40-nm CMOS technology, the implemented true time delay achieves maximum 900ps delay at 3GHz and 500ps delay at 6GHz with 0.15% variation. Reliability of the design is verified by process variation simulation as well. The proposed topology provides a large delay range with a compact size, which is suitable for sub-6 GHz wideband applications.

Detection distance is a critical specification in automotive driving. The output power of a power amplifier is the bottleneck for the detection range. In this work, a design of 77 GHz power amplifier is presented in a 40 nm CMOS technology with a four-way parallel-series power combing technique for achieving a 20 dBm output power (Psat), which meets a 186-meter detection range in the conditional of 30 mm/h rainfall capacity. In this parallel-series power combing technique, distributed active transformers perform load-pull matching and in-phase power combining. It achieves a compact solution for future on-chip antenna integration. This PA is optimized for maximal power-added efficiency of 21.35% with 20 dBm saturated output power at 77 GHz.

High Performance Wireless Sensor Networks (HP-WSN) for critical, low latency applications such as traffic control, industrial process control, smart structures and smart vehicles has been a fast-growing field. Nevertheless, efforts towards new systems and circuit architectures to enable real-time, predictable and reliable HP-WSN have been limited, specially for reliable, low latency wireless links. This paper presents for the first time, to authors' knowledge, a low power, wideband, large delay, tunable, compact, CMOS-scalable and frequency-independent true time delay cell that enables wideband beamforming on HP-WSN. This new architecture, inspired on bucket brigade devices and N-path structure, is especially well suitable for sub-3 GHz ISM bands, where most of WSN transceivers work. Post-layout simulations of a circuit demonstrator has shown a continuous time delay between 100 - 1000 ps with 0.5% delay variation over 0 - 3 GHz band. The layout area is only 0.025 mm2and it consumes 10 - 19 mW, including buffers. It has also established a record of delay-per-area density of 40000 ps/mm2.

The sampling nature of the phase-frequency detector (PFD) degrades the stability of the charge-pump phase-locked loop (CPPLL). This paper analyzes the effect of the PFD sampling on the CPPLL stability by using z-transform. The PFD is modeled as a zero-order hold to perform the z-domain analysis. The stability boundary predicted by the analysis is accurate and verified by simulations using Cadence Spectre. In addition, a physical interpretation of how sampling destabilizes an otherwise stable continuous feedback system is provided in time domain, which brings valuable insight into the operation of sampled feedback systems like CPPLL.

This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2ndharmonic cancellation to reduce output ripple while achieving high detection speed at the same time. The envelope detector operates from 500MHz to 6GHz with a detection speed of 250 MHz. It achieves less than 2% ripple, 0.64 ns delay and consumes 76.9 uW. With the achieved results, it is suitable for use in a nonlinear interference suppression receiver, enabling more than 25 dB of suppression.

The phase noise of a phase-locked loop (PLL) has a great impact on the performance of frequency-modulated continuous-wave (FMCW) radar. To examine the effects of the phase noise on FMCW radar performance, a model of an FMCW radar with a noisy PLL is developed. A filter-based technique for modeling the PLL phase noise is described. The radar model shows that PLL in-band phase noise affects the spatial resolution of the FMCW radar, whereas PLL out-of-band phase noise limits the maximum range. Finally, we propose a set of design constraints for PLL based on the model simulation results.

A new wideband beam steering architecture for a receiver and transmitter is proposed. In this new interpolation based beam steering architecture (IBA), the number of true time delays can be dramatically reduced to 3 for a 2-dimensionaI array and 2 for a linear array independent of the number of array elements. While in conventional phased arrays, the number of phase shifters or time delays equals the number of antenna elements. This is achieved by representing individual antenna signals through a weighted sum of base vectors. In this paper, the system level implementation of the interpolation based beam steering architecture for the transmitter and receiver is presented. Also, trade-offs between number of time delays, array factor and the bandwidth of an N-element antenna array are discussed. The new architecture is expected to be relevant for the large beam steering arrays in 5G and beyond 5G wideband communication systems By using this method, the area, loss and complexity of a beam steering system can be reduced.

In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.

In this paper the architecture and performance of a co-integrated 60 GHz on-chip wireless energy harvester and ultra-low power (ULP) radio in 65-nm CMOS are discussed. Integration of an on-chip antenna with wireless power receiver and wireless data transfer module is the crucial next step to achieve compact and high efficiency fully-integrated monolithic wireless sensor nodes. A single-pole-single-throw 60 GHz RF switch is proposed and simulated to decouple the power harvesting and data transfer module. The designed on-chip RF switch has -2 dB insertion loss in EM simulations, and achieves -18 dB isolation between the energy harvesting module and the data transfer module. A single on-chip monopole antenna for power reception and data transfer is proposed with an adapted layout to reduce power coupling to undesired substrate modes. The simulated antenna shows a gain of -1.68 dBi. The power harvesting performance of the co-integrated antenna, switch and Dickson type multistage rectifier is simulated and leads to a DC output voltage of 1.2 V for -5 dBm input power at 60 GHz. With 15 dBm power transmitted to the tag at 30 GHz, the output voltage is 1.14V in the measurement. This paper is the first to demonstrate the 30 GHz mm-wave wireless energy harvesting with fully on-chip wireless energy receiver.

Monolithic wireless sensors with integrated antenna, on-chip transceiving, sensing and energy scavenging are low-cost and robust, thus very suitable for mass production and deployment. The design of such a sensor node requires a proper architecture with careful trade-offs and joint considerations over different building blocks. In this paper, we focus on the energy scavenging and receiver part of such a sensor node. A radio-triggered receiver architecture is proposed to achieve the extreme low energy budget. Energy/power models for different building blocks are developed that show the tradeoffs between available energy and sensor performance. A system-level analysis identifies the 60GHz mm-wave band is suitable for such applications. Moreover, a design example of receiver front-end in 65nm CMOS technology is presented to demonstrate the potential performance of the proposed architecture.

This paper presents the design of a 60-GHz rectenna with an on-chip antenna and rectifier in 65nm CMOS technology. The rectenna is often the bottleneck in realizing a fully-integrated monolithic wireless sensor tag. In this paper, problems of the mm-wave rectifier are discussed, and the self-threshold voltage modulation method is proposed for better sensitivity and efficiency. Based on this discussion, the design of a 60 GHz rectenna is provided. The designed on-chip antenna has 2 dBi gain at 60 GHz. The designed rectifier reaches 4.4% efficiency with 7 dBm input power with a 1.5 kΩ load in simulation.

RF energy scavenging enables batteryless operation of wireless sensors. In particular, a system with a central controller that transfers wireless energy to and exchanges information with RF energy scavenging sensors is very suitable for a wide range of applications. State-of-the-art analysis of RF energy scavenging is mostly based on RF-DC rectifier models operating with relatively high input power to achieve high rectification efficiency. However, to enable larger distance between the central controller and sensors and/or to increase the operating frequencies, which can lead to small and low-cost smart dust like sensors, a good model describing the RF-DC rectification with low input power is needed to aid system design and optimization. In this paper, we develop such a model. Using the model, we derive closed-form solutions for the equilibrium voltage and the input resistance of the rectifier. We further propose a quasi-static model to describe the dynamic charging of the capacitor in the rectifier. A comparison with circuit simulations using Cadence Virtuoso Spectre circuit simulator shows good match between our model and the circuit simulation.