Michal Servít

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3ranked-venue papers

3as first author

0since 2021 · last 1991

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

2 papers

Integrated circuit design · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Integrated circuit design digital circuit design	2	1975	Hazard Correction in Synchronous Sequential Circuits · IEEE Trans. Computers 1975 Hazard Correction in Asynchronous Sequential Circuits Using Inertial Delay Elements · IEEE Trans. Computers 1973
Integrated circuit design › digital circuit design hazard correction	2	1975	Hazard Correction in Synchronous Sequential Circuits · IEEE Trans. Computers 1975 Hazard Correction in Asynchronous Sequential Circuits Using Inertial Delay Elements · IEEE Trans. Computers 1973
Integrated circuit design › digital circuit design › sequential circuit design synchronous sequential circuits	1	1975	Hazard Correction in Synchronous Sequential Circuits · IEEE Trans. Computers 1975
Integrated circuit design › digital circuit design › sequential circuit design asynchronous sequential circuits	1	1973	Hazard Correction in Asynchronous Sequential Circuits Using Inertial Delay Elements · IEEE Trans. Computers 1973
Integrated circuit design › digital circuit design inertial delay element	1	1973	Hazard Correction in Asynchronous Sequential Circuits Using Inertial Delay Elements · IEEE Trans. Computers 1973

Year	Publication	Venue	Position
1991	Strategy of one and half layer routing Michal Servít, Jan Schmidt	Microprocessing and Microprogramming	1
1975	Hazard Correction in Synchronous Sequential Circuits abstract Limitations which are placed on input and clock signals of single and double-rank synchronous sequential circuits with memory composed of level-triggered flip-flops are presented and compared with the results of Unger [1] and Curtis [2]. Michal Servít	IEEE Trans. Computers	1
1973	Hazard Correction in Asynchronous Sequential Circuits Using Inertial Delay Elements abstract This correspondence is concerned with the use of inertial delay elements for the correction of influences of aith-order hazards and races among internal signals on the activity of asynchronous sequential circuits. Michal Servít	IEEE Trans. Computers	1