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Marco Mezzalama

dblp:70/1286 · DBLP profile ↗
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17ranked-venue papers
7as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 4 first-authorSoftware engineering, systems software and programming languages · 3 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 2Artificial intelligence and machine learning · 1Security and privacy · 1Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 91% Processor architecture and microarchitecture · 9%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.031985
Testing Strategy and Technique for Macro-Based Circuits · IEEE Trans. Computers 1985
PART: Programmable Array Testing Based on a Partitioning Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
A new integrated system for PLA testing and verification · DAC 1983
Electronic design automation › hardware verification and test
test generation
0.021985
Testing Strategy and Technique for Macro-Based Circuits · IEEE Trans. Computers 1985
PART: Programmable Array Testing Based on a Partitioning Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Electronic design automation › hardware verification and test › VLSI testing
programmable logic array testing
0.021984
PART: Programmable Array Testing Based on a Partitioning Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
A new integrated system for PLA testing and verification · DAC 1983
Electronic design automation › hardware verification and test
design for testability
0.011985
Testing Strategy and Technique for Macro-Based Circuits · IEEE Trans. Computers 1985
Electronic design automation
logic synthesis
0.011985
Testing Strategy and Technique for Macro-Based Circuits · IEEE Trans. Computers 1985
Electronic design automation › logic synthesis
programmable logic array
0.011985
Testing Strategy and Technique for Macro-Based Circuits · IEEE Trans. Computers 1985
Electronic design automation › hardware verification and test › test generation
compact test sets
0.011984
PART: Programmable Array Testing Based on a Partitioning Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Processor architecture and microarchitecture
microprogramming
0.011983
A Hierarchical Description Model for Microcode · IEEE Trans. Computers 1983

Methods — techniques the papers use, named apart from their topics

heuristics · 0.0topological propagation · 0.0partitioning algorithm · 0.0integrated test system · 0.0formal modeling · 0.0algebraic signal propagation · 0.0
YearPublicationVenuePosition
2017 Experimental Validation of a Massive Educational Service in a Blended Learning Environment
abstract
New information and communication technologies offer today many opportunities to improve the quality of educational services in universities and in particular they allow to design and implement innovative learning models. This paper describes and validates our university blended learning model, and specifically the massive educational video service that we offer to our students since 2010. In these years, we have gathered a huge amount of detailed data about the students' access to the service, and the paper describes a number of analyses that we carried out with these data. The common goal was to find out experimentally whether the main objectives of the educational video service we had in our mind when we designed it, namely appreciation, effectiveness and flexibility, were reflected by the users' behavior. We analyzed how many students used the service, for how many courses, and how many videos they accessed within a course (appreciation of the service). We analyzed the correlation between the use of the service and the performance of the students in terms of successful examination rate and average mark (effectiveness of the service). Finally, by using data mining techniques we profiled users according to their behavior while accessing the educational video service. We found out six different patterns that reflect different uses of the services matching different learning goals (flexibility of the service). The results of these analyses show the quality of the proposed blended learning model and the coherency of its implementation with respect to the design goals.
Elena Baralis, Luca Cagliero, Laura Farinetti, Marco Mezzalama, Enrico Venuto
COMPSAC (1)4
2017 Educational video services in universities: A systematic effectiveness analysis
abstract
Our university has offered a massive educational video service since 2010, as part of a blended learning model that allows students to balance active participation in the classroom with remote access to video-recorded lectures. In these years, we have collected a huge amount of very detailed data about the students' access to the service. Together with additional information that characterize a university system (e.g. students' performance or course population), these data represent a precious ground set to assess the educational model. The paper describes an experimental set to profile the use of the educational video service, whose results will contribute to improve the model. Specifically the paper analyzes the students' service use relatively to different transversal course characteristics, such as level, main topic, population, success rate. As a result, it outlines the profile of the “ideal” courses for which students highly appreciate the service. This information will help educational designers to select the future courses to be included in the service, but it will also give directions on the sectors where improvements are necessary. Finally, the paper experimentally demonstrates a positive impact of the educational video service on students' performance, and specifically on the exam success rate.
Luca Cagliero, Laura Farinetti, Marco Mezzalama, Enrico Venuto, Elena Baralis
FIE3
1997 Secure document management and distribution in an open network environment
Antonio Lioy, Fabio Maino, Marco Mezzalama
ICICS3
1986 Scanning the issue
Bernard Courtois, Marco Mezzalama
Proc. IEEE2
1985 Testable design with PLA macros
Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
Microprocessing and Microprogramming3
1985 Dynamic Storage Allocation: Experiments Using the C Language
abstract
Abstract The paper discusses the problem of dynamic storage allocation (DSA) using C in a VMS environment. The problem is studied in a specific context, i.e. fault simulation of logic circuits. However, owing to its intrinsic generality, the adopted solution can be effectively applied to a large number of similar situations. It is shown how the use of standard C‐functions for dynamic memory allocation result unacceptable for efficiency reasons and different implementation strategies to solve the problem are presented.
Silvano Gai, Marco Mezzalama
Softw. Pract. Exp.2
1985 Testing Strategy and Technique for Macro-Based Circuits
abstract
The increasing complexity of VLSI systems demands structured approaches to reduce both design time and test generation effort. PLA's and scan paths have both been widely reported to be efficient in this sense. This correspondence presents an easily testable structure and its related testing strategies. The circuits are assumed to be based on the interconnection of combinatorial macros, mostly implemented by PLA's; tests are generated locally, considering the involved macro as an isolated item, and then are expressed in terms of primary inputs and outputs using a topological approach as general strategy and algebraic techniques for the propagation of signals through macros. Propagation is dealt with by new algorithms. Since the problem of test generation is NP-hard, a set of heuristics is introduced to keep the amount of computation reasonable; several implementation issues are finally investigated.
Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
IEEE Trans. Computers3
1984 Microprogram simulation using a structured microcode model
Marco Mezzalama, Paolo Prinetto
Microprocessing and Microprogramming1
1984 PART: Programmable Array Testing Based on a Partitioning Algorithm
abstract
PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.
Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1983 A new integrated system for PLA testing and verification
Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
DAC3
1983 A Hierarchical Description Model for Microcode
abstract
In the paper, a structured and formal way to define microcode and to model a microprogrammed machine in terms of microoperations and their collection in microinstructions is proposed. It is characterized particularly by the hierarchical subdivision of microcode modeling, associated with the introduction of proper formalism to describe each level and the representation of both hardware timing and resource specification (with respect to their hardware characteristics and utilization in the architecture) in a completely machine-independent way.
Marco Mezzalama, Paolo Prinetto
IEEE Trans. Computers1
1982 A Machine-independent Approach to Microprogram Synthesis
abstract
Abstract The paper addresses the problem of automating microprogram generation, starting from a high‐level language (namely from a subset of PL/1). The microprogram synthesis process is structured in four steps in a highly hierarchical way; each step may be viewed as an independent process which uses formal representations for both data (i.e. the input program) and machine specifications. The translation system is based on a microcode model built on a formal definition of microoperations, microinstruction semantics, and relationships among microinstructions.
Marco Mezzalama, Paolo Prinetto
Softw. Pract. Exp.1
1981 A strategy for simulating bit-slice based microprogrammable systems
Marco Mezzalama, Paolo Prinetto
Microprocessing and Microprogramming1
1979 A microprocessor based audio response system
abstract
In this paper a low-cost, small dimensions, multiple users audio response system using microprocessors and LSI circuits is presented, The synthesis strategy is performed by a MOS microprocessor, which provides 12 LPC parameters to a microprogrammable digital filter. The synthetic message is produced by a concatenation of units which range from words to dyad-like elements, depending on the application. The synthesis algorithm is based on two main steps: the segment concatenation rules and the prosodic rules. The fundamental frequency contour is defined by the type of sentence, the punctuation ma rks and the position of the accents.
Marco Mezzalama, Angelo Serra
ICASSP1
1978 A microprocessor executive for real-time process control
Marco Mezzalama, Pietro Torasso
Euromicro Newsletter1
1977 A syntactic procedure for the recognition of glottal pulses in continuous speech
Renato De Mori, Pietro Laface, V. A. Makhonine, Marco Mezzalama
Pattern Recognit.4
1976 Automatic generation of pitch contour for speech synthesis
abstract
The rules for the generation of the pitch contour of a fragment of the Italian language are presented. The generative model, of which the input is a formal description of the sentence and outputs the pitch contour, operates as an automaton. The basic elements for the pitch curve generation are the segments between two accents. Inside these segments the pitch curves is approximated by means of simple primitives. The pitch rules are used to control a digital speech synthesiser.
Marco Mezzalama, Enrico Rusconi, Pietro Torasso
ICASSP1