Demo Data from EDBT 2026 / reviewers in the wild / expert
Kai-Yu Chu
dblp:70/1539
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.0 | 1 | 1988 | A Single Chip Parallel Multiplier by MOS Technology · IEEE Trans. Computers 1988 |
Integrated circuit design › digital circuit design › arithmetic circuit design
parallel multiplier |
0.0 | 1 | 1988 | A Single Chip Parallel Multiplier by MOS Technology · IEEE Trans. Computers 1988 |
Integrated circuit design › semiconductor devices
MOS technology |
0.0 | 1 | 1988 | A Single Chip Parallel Multiplier by MOS Technology · IEEE Trans. Computers 1988 |
Methods — techniques the papers use, named apart from their topics
pass-gate logic · 0.0five-counter cell design · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | A Single Chip Parallel Multiplier by MOS TechnologyabstractA parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication (approximately twice as fast as that of the full adder design) with a moderate increase in hardware complexity. With the five-counter design, an improvement in the hardware complexity of a squarer can be expected.> Shinji Nakamura, Kai-Yu Chu |
IEEE Trans. Computers | 2 |