Nyquist, in his seminal paper published almost a hundred years ago, showed that the voltage noise spectral density of a one port consisting of resistors, capacitors and inductors is given by 4kT Re(Z(j2πf)) where Z(j2πf) denotes the driving-point impedance of the one port. In this work, we derive a result for one ports that consists of inductors, capacitors, resistors and periodically-operated switches. The derivation exploits power conservation and the properties of adjoint linear periodically time-varying (LPTV) networks.

The continuous-time pipeline(CTP) ADC is an emerging architecture that realizes the equivalent of an anti-alias filter followed by a Nyquist-rate ADC. This work analyzes the effect of weak amplifier nonlinearities on the performance of a filter+ADC chain and compares it with that of an equivalent CTP. For a given power dissipation and noise, we show that an appropriately designed CTP is more linear when compared to a filter+ADC cascade. Our theory is verified using macro-model and transistor-level simulations.

Circuits that generate a current or voltage proportional to absolute temperature are referred to as PTAT generators. Such circuits form the core of bandgap voltage references. This work derives textbook PTAT generator circuits from first principles, and shows these ideas can be used to generate alternative circuits.

This paper presents a new architecture for bandpass delta-sigma modulators (BP$\Delta \Sigma $Ms) featuring finite impulse response (FIR) filters in the feedback path. The effectiveness of FIR feedback in lowpass delta-sigma modulators (LP$\Delta \Sigma $Ms) has been well-established in improving loop-filter linearity and robustness to clock jitter. Building upon these findings, we explore the application of bandpass FIR filters in single-bit BP$\Delta \Sigma $Ms. By contrast to conventional BP$\Delta \Sigma $Ms, the proposed technique significantly reduces out-of-band quantization error contents in the feedback signal. This approach is applicable to both discrete-time and continuous-time implementations. Further, we show that performance does not improve by increasing the number of FIR taps beyond a certain point. However, we can enhance filtering performance by employing non-equal coefficients within the filter. To validate the efficacy of the presented approach, the paper includes electrical simulation of a 4th-order active-RC BP$\Delta \Sigma \text{M}$.

This paper investigates finite impulse response (FIR) feedback in bandpass delta-sigma modulators (BP-$\Delta \Sigma \text{Ms}$). FIR feedback in lowpass delta-sigma modulators (LP-$\Delta \Sigma \text{Ms}$) improves loop filter linearity and reduces the sensitivity of the modulator to clock jitter. We show that similar benefits can be obtained in a BP-$\Delta \Sigma \mathrm{M}$if the FIR filter in the feedback path is made a bandpass one11This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by “Junta de Andalucía” under Grant P20-00599 and in part by the Center of Excellence in RF, Analog and Mixed-Signal ICs (CERAMIC), IIT Madras..

The continuous-time pipelined (CTP) analog-to-digital converter is a power-efficient realization of an anti-alias filter and ADC cascade. Digital reconstruction is a key aspect that determines the performance of the CTP. Ideally, these filters have an infinite impulse response (IIR), but in practice are realized using their FIR approximations. This work investigates the influence of finite length and precision of the reconstruction FIR filters on the performance of the CTP. The theory is supported by measurement results from two three-stage CTPs designed in a 65 nm CMOS process. One of the converters achieves 74dB, whereas the other achieves a 70dB SNDR in a 100MHz bandwidth while sampling at 800MHz.

The continuous-time pipelined (CTP) analog-to-digital converter is an emerging architecture that realizes the equivalent of an anti-alias filter followed by an ADC. This work compares power-noise trade-offs in CTPs with those in a filter+ADC cascade. We consider two commonly-used filter topologies, namely the Tow-Thomas and Rauch biquad structures. We show that the SNDR of an appropriately designed CTP is much higher than that achieved by a signal chain consisting of an active filter driving a Nyquist ADC. Our theory is verified using macro-model and transistor-level simulations.

We present a systematic treatment of reciprocity and inter-reciprocity in linear electrical networks, without resorting to the use of Tellegen’s theorem. In Part I, we discuss linear time-invariant networks. In Part II, we expand the applications of our approach to linear periodically time-varying (LPTV) networks.

The second part of this two-part paper addresses reciprocity in linear periodically time-varying (LPTV) networks. We first give a brief overview of LPTV circuits and systems Using this, we derive the adjoint network, which naturally leads to the intriguing concept of time-reversal in the adjoint network. The frequency-reversal and transfer-function theorems are then derived. Finally, we derive some useful properties of LPTV circuits with sampled outputs. The theory is illustrated with examples.

We investigate the performance degradation of a continuous-time pipelined (CTP) ADC due to the input load presented by the flash sub-converter. It turns out, as we show in this work, that the flash ADC loading affects the alias rejection and the linearity of the CTP. We propose a simple technique to alleviate these problems. The theory is borne out by simulation results from a 100 MHz-bandwidth pipeline ADC designed in a 65 nm CMOS process.

The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at$f_{s}\,{=}\,800$MHz, while the back-end samples at$f_{s}/2$.

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s.

We describe the design principles behind an all-analog, neural-network-based voice activity detector (VAD). Our architecture, which uses a neural engine with weights that only take on values -1,0 and 1, achieves high accuracy along with low latency. Implemented in a 130 nm CMOS process, the VAD consumes 28.5 μW from a 1.8 V supply and achieves a latency of only 10 ms. The measured hit rate for speech(non-speech) is 94.3%(94.1%).

Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator's linearity, reducing the quantizer's complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In the incremental mode, however, the maximum stable amplitude of the ADC is severely impacted by FIR feedback. The reasons behind this are examined, and techniques that mitigate this problem are given. Circuit simulations of an example fourth-order single-bit incremental modulator with an eight-tap FIR DAC are given to illustrate the efficacy of the theory.

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CTDSM). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, like settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This work gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given.

We show that the nonlinearity of the first integrator's operational transconductance amplifier (OTA) significantly degrades the alias rejection of a bandpass CTΔEM in the presence of OTA parasitics. We derive the expression for alias rejection when the OTA used in the first integrator is realized as a two stage feed-forward compensated structure. Simulation results confirm the theory.

The total integrated noise in passive switched-capacitor and N-path filters is traditionally calculated using frequency-domain methods. We derive a technique that allows the determination of the total noise in such networks by inspection. The key aspect of our derivation is to exploit the properties of sampled linear periodically-switched networks, and to work in the time domain. Simulation results that support our analysis are given.

A novice continuous-time delta-sigma designer is faced with an admittedly complex maze of possible design choices. The right architecture often determines how efficiently the modulator can be implemented. This paper critically examines various popular delta-sigma architectures. It concludes that a single-bit modulator with FIR feedback is a prime candidate that enables a power-efficient implementation for a variety of specifications. To support this thesis, measurement results of an audio delta-sigma modulator, designed in a 65 nm CMOS process are given. The modulator, which incorporates FIR feedback and chopping to reduce 1/f noise, achieves 98.6 dB peak SNDR in a 24 kHz bandwidth and consumes only 260 μW from a 1.2 V supply.

We show that the output of a linear periodically time-varying (LPTV) system varying with frequency ωs, when driven by an input of the form Σka[k]δ(t - kTs), where Ts= 2π/ωs, is indistinguishable from the output of an appropriately chosen linear time-invariant filter driven by the same input. We extend this result, and give an expression for the transfer function of the equivalent time-invariant filter. We apply this principle to the design of a smoothing filter that follows a digital-to-analog converter. We show that using an LPTV smoothing filter rather than a time-invariant one not only results in better image attenuation, but can also avoid group-delay distortion.

Using a switched capacitor DAC in the feedback path of a continuous-time ΔΣ modulator reduces the sensitivity of the modulator to clock jitter. However, the peak to average ratio of the feedback waveform is large, thereby degrading the linearity of the modulator. The recently proposed dual switched capacitor resistor (DSCR) DAC aims to address this problem. This brief analyzes some interesting properties of this DAC, which have not been recognized in prior work. In particular, we show that using an DSCR DAC has excellent alias rejection around odd multiples of the sampling frequency. The intuition, theory and simulations that confirm this phenomenon are given.1

Monitoring the eye diagram at the output of an embedded analog adaptive equalizer used in a high speed serial link is challenging. Eye measurement using an external oscilloscope is problematic due to the bandwidth of the test setup. In this work, we describe the working principle and design details of a low cost, on-chip monitor circuit that enables the determination of the eye diagram. The eye opening monitor (EOM), implemented in a 65 nm CMOS process, occupies 0.06 mm2and consumes 5.7 mW from a 1.2 V supply. Measurements demonstrate the efficacy of our techniques.

UWB pulse waveforms based on modified Hermite polynomials are spectrally efficient and mutually orthogonal. A reconfigurable generation of these UWB signals is a challenge. In this work, we present a programmable pulse shaping filter based on singly-terminated LC ladders. By appropriate setting of the filter taps, a variety of shapes related to a Gaussian pulse can be generated. Experimental results from a test chip designed in a 0.25 μm BiCMOS process are given.

Determining the Noise and Signal Transfer Functions (NTF and STF) of a Continuous-Time Delta-Sigma Modulator (CTDSM) is an important aspect of the design verification process. In several practical CTDSM designs, like those with Switched Capacitor (SC) and Return-to-Open (RTO) feedback DACs, the loop filters are time varying, rendering traditional methods incorrect and/or time consuming. In this work, we exploit the linearity of the loop filter to determine the Signal and Noise Transfer Functions (NTF) of a modulator using time domain techniques that need far less simulation time than conventional methods.

Characterizing wide band continuous-time ΔΣ modulators is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. Experimental results from a single-bit CTDSM operating at 4.4 GHz are given, demonstrating the efficacy of the technique.

We analyze in-band thermal noise in continuous-time delta sigma modulators (CTDSMs) with Switched-Capacitor feedback DACs. We show that in such modulators, noise from around multiples of the sampling frequency aliases to in-band frequencies. We give an intuitive understanding of this phenomenon and describe a model that can be used to analyze noise in such modulators. We present the results obtained using state space analysis. Our results compare well with those obtained from a circuit simulator.

Continuous-time Delta Sigma Modulators (CTDSM) have "Implicit Anti-Aliasing" is a commonly heard refrain in the data-converter design community. We show that this is not the case when a switched capacitor (SC) feedback DAC is used, thereby nullifying one of the principal advantages of continuous-time operation. We give an intuitive understanding of this phenomenon, and propose a power efficient circuit technique to improve alias rejection.

We propose a technique that enables a designer to study the effect of weak loop filter nonlinearities in a class of continuous-time delta-sigma modulators. Thanks to this technique, the utility of the Schreier Delta-Sigma Toolbox can be extended to include weakly nonlinear effects, enabling the architectural exploration of alternate loop filter and opamp topologies. The results from the use of our technique are compared to those obtained using a circuit simulator, and good agreement is seen.

We describe the design of a fifth order opamp-RC filter in a 65nm digital CMOS process. Designed for a WLAN receiver chain, the baseband filter has a bandwidth of 9MHz and features extensive use of digital hardware to correct for analog imperfections and thereby relaxing area and power requirements. Measurements show a 24 dB adjacent channel attenuation and an out-of-band IIP3 of 33 dBm. The complete filter consumes 9.5mA from a 1.3V supply and occupies an area of 0.46mm2.

We describe an in-situ analog technique for estimating time constant shifts in continuous-time single bit delta-sigma modulators. We show that the variance of the first integrator output of the modulator's loop filter is a good indicator of RC time constants. The nominal values of the time constants are restored by digitally controlling the resistance and capacitance values (realized as switched banks). Simulation results that demonstrate the efficacy of the time-constant tuning system are given for a third order CIFF modulator.

We present a low power analog adaptive equalization technique suitable for combating inter-symbol-interference at very high data rates. The proposed technique, which we term the continuous time equalizer (CTE), addresses several limitations associated with equalizers based on tapped delay lines. The theory and circuit implementations are given. Simulations comparing the CTE with ideal tapped delay line filters are shown.

The authors apply the "space-mapping" optimization for design centering high frequency integrated continuous-time filters. Graphical intuition is given to better understand a simplified version of the space-mapping technique. An example of a fifth order 70-500 MHz constant-C scaled Gm-C Chebyshev ladder filter, designed in a 0.35μm CMOS process is presented to illustrate the method.

We show that transmission line based FIR filters built using singly terminated delay lines can perform as well as travelling-wave structures (with a fraction of the power dissipation), provided resistive shunt compensation is employed to cancel the effects of series loss in the transmission lines. The problem of an unwieldy aspect ratio of a transversal filter when laid out on an integrated circuit is avoided by employing a class of structures called bi-transversal filters. The electrical equivalence between singly-terminated and bi-transversal filters is proved, and we conclude that these form excellent candidates for the LMS algorithm based adaptive equalization at gigabit speeds.

We examine noise due to clock jitter in single-loop low pass continuous-time delta-sigma modulators employing NRZ feedback DACs. Using the discrete-time version of the Bode sensitivity integral, we derive a lower bound on jitter noise and its relationship to the noise transfer function of the modulator. We give intuition to a recent observation (arrived through numerical optimization) that NTFs with peaking in their pass bands have lower jitter noise than maximally flat NTFs.

Variants of conventional transmission line based transversal and traveling wave FIR structures are proposed and their performance is compared with respect to nonidealities in the transmission lines. New topologies for FIR filters, called bi-transversal structures, are presented. Shunt compensation is shown to be a useful technique for improving the performance of all families of transmission line based filters.