Testing at-speed delay defects is difficult on a speed constrained low cost tester. This paper describes the use of a clock chopper based onproduct clocking circuitry and interfaces to delay ATPG to achieve reliable test patterns. We also describe the test compression methods used to address the problem of increased test data volume due to delay tests. Data is presented on several industrial circuits to demonstrate the effectiveness of these DFT methods on nanometer designs. Our results show that a seamless combination of atspeed delay testing with compression can help to test the nanometer defects at a very competitive cost.

This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, \DeltaIddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of \DeltaIddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, and considers interaction between, static, \DeltaIddq, dynamic, and memory BIST defects. Defect density and defect level are also reported based on the new method.

The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architectures: table-look-up and multiplexor-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources.