In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realized? Here, we describe the European logarithmic microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful, and that for 32-bit work, logarithmic arithmetic may now be the technique of choice.

An architecture design is presented for a device based upon the logarithmic number system (LNS) that is capable of performing general matrix and complex arithmetic, with features useful for DSP system-on-chip applications. A modified LNS addition/subtraction unit is employed in multiple execution units to achieve a maximum single-precision floating-point (FP) equivalent throughput of 3.2 Gflop/s at a clock frequency of 200 MHz. Each execution unit is capable of computing functions of the form (ab + cd)/sup e/ for e /spl isin/ {/spl plusmn/0.5, /spl plusmn/1, /spl plusmn/2} in a 5-stage arithmetic pipeline and returning a result every cycle, yielding a considerable per-cycle improvement over both floating- and fixed-point systems. Comparisons with existing devices and a single floating-point unit are given.

A new European research project aims to develop a microprocessor based on the logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage over floating-point if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-point, but these operations require the interpolation of a nonlinear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately and show that these operations are thereby competitive with their floating-point equivalents. We then present some large-scale case studies which show that the average performance of the LNS exceeds floating-point, in terms of both speed and accuracy.

As an alternative to floating-point, several papers have proposed the use of a logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-paint, but these operations require the interpolation of a non-linear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately, and show that these operations are thereby competitive with their floating-point equivalents. We then show that the average performance of the logarithmic system exceeds floating-point, in terms of both speed and accuracy.