This keynote is a tribute to the late Prof. Mel Breuer, entitled Contributions to CAD and Test. It is organized by Sandeep Gupta. A panel of three prominent speakers gives this keynote. The three speakers are Miron Abramovici, Magdy Abadir and Sridhar Narayanan.

We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verication of hardware designs is the need to manually specify design-specic properties. IODINE presents a way to automatically extract properties such as state machine protocols, request-acknowledge pairs, and mutual exclusion between signals from design simulations. We show that dynamic invariant detection for hardware designs can infer relevant and accurate properties.

In this paper, we describe TSOtool, a program to check the behavior of the memory subsystem in a shared memory multiprocessor. TSOtool runs pseudo-randomly generated programs with data races on a system compliant with the total store order (TSO) memory consistency model; it then checks the results of the program against the formal TSO specification. Such analysis can expose subtle memory errors like data corruption, atomicity violation and illegal instruction ordering. While verifying TSO compliance completely is an NP-complete problem, we describe a new polynomial time algorithm which is incorporated in TSOtool. In spite of being incomplete, it has been successful in detecting several bugs in the design of commercial microprocessors and systems, during both pre-silicon and post-silicon phases of validation.

The scan chain needs to operate correctly to utilize the scan features in a design. The presence of defects in the chain can invalidate the test and debug methodology for a design. In this paper we present a novel strategy to efficiently diagnose a scan chain. The main idea is to add circuitry to a scan flop to enable its scan-out port to be either set or reset. Use of this circuitry requires no additional control signals, and has no impact on the timing of the design. Based on this set/reset feature, we then present a global strategy to efficiently incorporate it in a scan design. This strategy takes into account disparities in the defect probabilities and controllability/observability attributes of flops in a scan chain. An algorithm to optimally modify a subset of the flops to maximize diagnostic resolution is described. Experimental results on two devices highlight the advantages of the proposed strategy.

This paper describes the testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor. Due to the aggressive nature of this high performance design, these three areas needed to be addressed at the beginning of the project to ensure success. We present the goals and analysis that lead to our decisions as well as the actual features that were implemented. The features described in this paper have helped enormously in achieving the time-to-volume goals and hence the overall success of the product.

The long test application times needed for scan designs increase the costs of testing. In this paper we introduce the concept of asynchronous multiple scan chains in which groups of scan chains operate independently. This is achieved by using more than one made signal to control the scan flip-flops. Asynchronous multiple chains can provide large reductions in the test application time. We present an efficient test application scheme to exploit the asynchronous operation of the chains. Based on this scheme, we outline techniques to configure the chains so as to minimize the test time. Implementation results show significant savings in test application time and highlight interesting design tradeoffs between the control complexity, I/O pin count and test time.

A major drawback in using scan techniques is the long test application times incurred in shifting test data in and out of a device. This problem assumes even greater significance with the rapid growth in both the number of test patterns and scan registers occurring in complex VLSI designs. This paper presents a novel methodology based on reconfiguring a single scan chain to minimize the shifting time in applying test patterns to a device. The main idea is to employ multiplexers to bypass registers that are not frequently accessed in the test process and hence reduce the overall test application time, For partitioned scan designs, we describe two different modes of test application which can be used to efficiently tradeoff the logic and routing overheads of the reconfiguration strategy with the test application time. In each case we provide detailed analysis and optimization techniques to minimize the number of added multiplexers and the corresponding test time. Implementation results on two data path circuits demonstrate test time reductions as large as 75% over traditional schemes at the expense of 1-3 multiplexers.>

A major drawback in using scan techniques is the long test application times needed to shift test data in and out of a device. This paper presents a novel methodology based on reconfiguring a single scan chain to minimize the shifting time in applying test patterns to a device. The main idea is to employ multiplexers to bypass registers that are not frequently accessed in the test process and hence reduce the overall test time. For partitioned scan designs, we describe two different modes of test application which can be used to efficiently tradeoff the logic and routing overheads of the reconfiguration strategy with the test application time. In each case, we provide optimization techniques to minimize the number of added multiplexers and the corresponding test time. Implementation results demonstrate test time reductions as large as 75% over traditional test schemes at the expense of 1-3 multipliers.

To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper, the authors consider the problem of optimally constructing the multiple scan chains to minimize the overall test time. Rather than follow the traditional practice of using equal length chains, the authors allow the chains to be of different lengths and show that this cap lead to lower test times. The main idea in this approach is to place those scan elements that are more frequently accessed in shorter scan chains as this tends to reduce the overall test time. Given a design with N scan elements and given that if scan chains need to be used for applying tests, the authors present an algorithm of complexity O(kN/sup 2/) for constructing the specified number of chains such that the overall test application time is minimized. By analyzing a range of different circuit topologies, the authors demonstrate test time reductions as large as 40% over equal length chains.>

The high test time for serial scan designs can be reduced by the use of multiple scan chains. The problem of optimally constructing multiple scan chains so as to minimize the overall test time is considered. Rather than following the traditional practice of using equal length chains, the chains are allowed to be of different lengths; this can lead to lower test times. The main idea of this approach is to assign those scan elements that are more frequently accessed to shorter scan chains. Given a design with N scan elements, and given that k scan chains are to be used for applying tests, an algorithm of complexity O(kN/sup 2/) is presented for configuring the chains such that the overall test application time is minimized. By analyzing a range of circuit topologies, test time reductions as large as 40% over equal length chain configurations are demonstrated.>