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Xiaole Xu

dblp:70/2763 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 2 first-authorSystems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 94% Integrated circuit design · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › fault modeling
crosstalk fault
0.011994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › hardware verification and test
fault modeling
0.011994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
hardware verification and test
0.011994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › hardware verification and test
test generation
0.011994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Integrated circuit design › parasitic capacitance
coupling capacitance
0.011994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
interconnect modeling
0.011994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

logic-level characterization · 0.0fault list generation · 0.0
YearPublicationVenuePosition
2017 A space-saving steering method for underwater gliders in lake monitoring
abstract
An increasing number of underwater gliders have been applied to lake monitoring. Lakes have a limited vertical space. Therefore, good space-saving capacity is required for underwater gliders to enlarge the spacing between monitoring waypoints. This paper presents a space-saving steering method under a small pitch angle (SPA) for appearance-fixed underwater gliders. Steering under an SPA increases the steering angle in per unit vertical space. An amended hydrodynamic model for both small and large attack angles is presented to help analyze the steering process. Analysis is conducted to find the optimal parameters of net buoyancy and roll angle for steering under an SPA. A lake trial with a prototype tiny underwater glider (TUG) is conducted to inspect the applicability of the presented model. The trial results show that steering under an SPA saves vertical space, unlike that under a large pitch angle. Simulation results of steering are consistent with the trial results. In addition, multiple-waypoint trial shows that monitoring with steering under an SPA covers a larger horizontal displacement than that without steering.
Yu-shi Zhu, Shi-jun Wu, Xiaole Xu
Frontiers Inf. Technol. Electron. Eng.5
2015 Observer-based consensus tracking for second-order leader-following nonlinear multi-agent systems with adaptive coupling parameter design
Xiaole Xu, Shengyong Chen, Lixin Gao 0004
Neurocomputing1
2013 Leader-following consensus of discrete-time multi-agent systems with observer-based protocols
Xiaole Xu, Shengyong Chen, Wei Huang 0015, Lixin Gao 0004
Neurocomputing1
1994 An approach to the analysis and detection of crosstalk faults in digital VLSI circuits
abstract
The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them.>
Antonio Rubio 0001, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3