Thermal issues of 3D-ICs have become increasingly severe in recent years. Thus, thermal simulation is needed to ensure thermal safety during the design stage. However, performing thermal simulation iteratively requires a significant amount of time. As a result, a fast and accurate method for thermal prediction is a promising alternative to improve the turnaround time. In this paper, we propose a fast thermal prediction method using machine learning models. In the training phase, we employ two models: one for the initial three time steps and another for the subsequent time steps. To enhance prediction accuracy, we introduce two types of features: spaced-windowed features and time-decayed features. These features help us to capture spatial and temporal information effectively. In our experiment, the mean absolute error for the predicted temperature is 1.12°C, and the maximum error is 7.27 °C. In the prediction phase, we achieve a 116X speed-up compared to a commercial tool. With our proposed method, users can predict transient thermal profiles quickly and accurately to ensure thermal safety.

This paper proposes a novel framework utilizing multimodal large language models (MLLMs) for referring video object segmentation (RefVOS). Previous MLLMbased methods commonly struggle with the dilemma between "Ref" and "VOS": they either specialize in understanding a few key frames (global reasoning) or tracking objects on continuous frames (local reasoning), and rely on external VOS or frame selectors to mitigate the other end of the challenge. However, our framework GLUS shows that Global and Local consistency can be Unified into a single video Segmentation MLLM: a set of sparse "context frames" provides global information, while a stream of continuous "query frames" conducts local object tracking. This is further supported by jointly training the MLLM with a pre-trained VOS memory bank to simultaneously digest short-range and long-range temporal information. To improve the information efficiency within the limited context window of MLLMs, we introduce object contrastive learning to distinguish hard false-positive objects and a self-refined framework to identify crucial frames and perform propagation. By collectively integrating these insights, our GLUS delivers a simple yet effective baseline, achieving new state-of-the-art for MLLMs on the MeViS and Ref-Youtube-VOS benchmark. Our project page is at https://glus-video.github.io/.

This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor. The proposed flow couples an IR-Informed Timing Optimizer with a Timing-Aware IR Optimizer to consider the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR-drop predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. We further propose Feature Approximation to speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.

In order to enhance the robustness of emergency communication systems, a Nyquist folding receiver (NYFR) assisted transceiver is designed to achieve reliable communication while sensing wideband electromagnetic environments in real time. However, one of the key issues is canceling the self-interference of communication transmitters on NYFR. Firstly, the proposed transceiver structure is presented in this paper, which utilizes the baseband signal of the communication transmitter as a reference signal to complete the reconstruction and cancellation of self-interference after spectrum compression. Considering the frequency offset between the self-interference reconstructed signal and the received signal, the impact on interference cancellation performance is theoretically analyzed based on the non-uniform discrete Fourier transform (NUDFT), and a closed-form expression for the self-interference cancellation ratio in NYFR is provided. The analysis and simulation results show that when the normalized frequency offset exceeds$3 \times 10^{-4}$, effective self-interference cancellation cannot be achieved.

Static chip thermal analysis provides detailed and accurate thermal profile on chip. The chip power map, commonly modeled as rectangular regions of distinct heat sources, significantly impacts the chip thermal profile. Since the heat sources result from numerous cells in functional blocks, the design space of chip power map is prohibitively enormous. Numerical simulations can be reliable for solving complex power maps; however, it could be very time-consuming when simulating a large SoC and/or 3DIC designs. Thus, there is an urgent need for speeding up the static chip thermal analysis to tackle various power maps. In this paper, we propose an approach of integrating our developed machine learning thermal solver [1] and decay curve characterization for solving static chip thermal with diverse power maps. The machine learning thermal solver would first solve the power maps on a coarse level (e.g., 200 um). The thermal results are further enhanced using the decay curve algorithm which would fine tune the solution locally provided by the machine learning thermal solver and calculate the local temperature variations at a finer level (e.g., 10 um). The deep learning models are trained on augmented artificial power maps and tested on realistic chip power maps. Experimental results validate the effectiveness of the proposed approach of offering fast and accurate chip thermal profile.

In single-input single-output (SISO) systems, transmitting the expected signals with artificially generated noise can effectively enhance the physical layer security (PLS). However, the traditional noise suppression at the intended receivers will increase algorithm complexity, particularly over multi-path fading channels, which poses challenges for some massive Internet-of-Things (IoT) networks that take advantage of low-cost and resource-constrained nodes. In this paper, we design a novel self-noise (SN) waveform for transmission security. The transmitter stacks the signal segments periodically, and the additive SN in the current signal period derives from the previous signal periods. Based on this, SN can be completely suppressed at intended receivers by differential operations between two adjacent signal periods. Both analysis and simulation results confirm that the proposed scheme can significantly reduce the complexity of noise suppression and its performance is not affected by multi-path channel environments. Besides, the proposed scheme can effectively worsen the signal-to-noise ratio (SNR) of eavesdroppers while having negligible impacts on intended receivers.

Cryptography hardware is vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. This article proposes simulation-based power and EM side-channel leakage analysis (SCLA) techniques on a cryptographic integrated circuit (IC) chip in system level assembly. SCLA measures SC leakage metrics including T-score, SC leakage score, and the number of measurement traces to disclosure, leveraged by a secure system-on-chip design flow toward SC attack resiliency and SC leakage sign off. Power SCLA features the tracking of security sensitive registers within cryptographic logic paths and the automatic assignments of probe points on associated physical power nets. Power supply current traces are efficiently simulated for the large set of input payloads, with direct vector-based and vector-less random switching controls. EM SCLA evaluates magnetic fields created by every piece of metal wiring in metal stacks where power supply current of cryptographic processing flows. The EM emission and EM SCLA from the backside Si surface of an IC chip in flip-chip packaging are experimentally examined with a 0.13 μm test chip. The proposed simulation-based SCLA exhibits the SC leakage metrics of on-chip location and direction dependency as accurately as in the measurements.

Accurate side-channel attacks can non-invasively or semi-invasively extract secure information from hardware devices using "side- channel" measurements. The thermal profile of an IC is one class of side channel that can be used to exploit the security weaknesses in a design. Measurement of junction temperature from an on-chip thermal sensor or top metal layer temperature using an infrared thermal image of an IC with the package being removed can disclose secret keys of a cryptographic design through correlation power analysis. In order to identify the design vulnerabilities to thermal side channel attacks, design time simulation tools are highly important. However, simulation of thermal side-channel emission is highly complex and computationally intensive due to the scale of simulation vectors required and the multi-physics simulation models involved. Hence, in this paper, we have proposed a fast and comprehensive Machine Learning (ML) augmented thermal simulation methodology for thermal Side-Channel emission Analysis (SCeA). We have developed an innovative tile-based Delta-T Predictor using a data-driven DNN-based thermal solver. The developed tile based Delta-T Predictor temperature is used to perform the thermal side-channel analysis which models the scenario of thermal attacks with the measurement of junction temperature. This method can be 100-1000x faster depending on the size of the chip compared to traditional FEM-based thermal solvers with the same level of accuracy. Furthermore, this simulation allows for the determination of location- dependent wire temperature on the top metal layer to validate the scenario of thermal attack with top metal layer temperature. We have demonstrated the leakage of the encryption key in an 128-bit AES chip using both proposed tile-based temperature calculations and top metal wire temperature calculations, quantified by simulation MTD (Measurements-to-Disclosure).

Harnessing unique physical properties of integrated circuits to enhance hardware security and IP protection has been extensively explored in recent years. Physical unclonable functions (PUFs) can sense inherent manufacturing variations as chip identifications. To enable the integration of PUFs into low-power and security applications, we study the impacts of process technology and supply voltage scaling on arbiter-based PUF circuit design. A Monte Carlo-based statistical analysis has demonstrated that advanced technologies and reduced supply voltage can improve the PUF uniqueness due to increased delay sensitivity. A linear regression approach has been leveraged to generate PUF delay profile by factoring in device, supply voltage and temperature variations. An accurate SVM-based software modeling analysis is used to verify the PUF additive delay behavior. Finally, postsilicon validation on arbiter-based PUF test chips in 45 nm SOICMOS technology has been correlated to simulation results and the inconsistency has been discussed. The test chips can resist the basic support vector machine attack due to the dynamic circuit effects and the limitation of our delay model.

Hardware Trojans have become a growing concern in the design of secure integrated circuits. In this work, we present a set of novel hardware Trojans aimed at evading detection methods, designed as part of the CSAW Embedded System Challenge 2010. We introduced and implemented unique Trojans based on side-channel analysis that leak the secret key in the reference encryption algorithm. These side-channel-based Trojans do not impact the functionality of the design to minimize the possibility of detection. We have demonstrated the statistical analysis approach to attack such Trojans. Besides, we introduced Trojans that modify either the functional behavior or the electrical characteristics of the reference design. Novel techniques such as a Trojan draining the battery of a device do not have an immediate impact and hence avoid detection, but affect the long term reliability of the system.

The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depends on minute uncontrollable process variations, a low supply voltage can benefit PUFs by providing high sensitivity to variations and low power consumption as well. Motivated by this, we explore the feasibility of sub-threshold arbiter PUFs in 45nm CMOS technology. By modeling process variations and interconnect imbalance effects at the post-layout design level, we optimize the PUF supply voltage for the minimum power-delay product and investigate the trade-offs on PUF uniqueness and reliability. Moreover, we demonstrate that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks. Our final 64-stage sub-threshold PUF design only needs 418 gates and consumes 0.047 pJ energy per cycle, which is very promising for low-power wireless sensing and security applications.

Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impact the data-dependent power of deep submicron cryptosystem designs. In this paper, we use Monte Carlo methods in SPICE circuit simulations to analyze the statistical properties of the data-dependent power with predictive 45nm CMOS device and ITRS process variation models. In addition to the "measurement to disclosure" (MTD) used in [3], we define a lower level metric, Power-Attack Tolerance (PAT), to model both dynamic power and leakage power data-dependence. We show that the PAT of a typical cryptographic component implementation using CMOS standard-cells can significantly deteriorate due to process variations, thus increasing the component's vulnerability to power attacks. Power-attack-resistant logic styles (e.g. SABL [9]) have been developed which increase PAT by an order of magnitude by balancing power consumption at the gate level with considerable overhead. However in the presence of process variations, the degradation probability of MTD is 57%. To mitigate this problem, we demonstrate a transistor sizing optimization method that can reduce such negative impacts to only 18% with minimal power and area overhead.

Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circuit foundries to covertly implant malicious hardware Trojans into a genuine design. Hardware Trojans provide back doors for on-chip manipulation, or leak secret information off-chip once the compromised IC is deployed in the field. This paper explores the design space of hardware Trojans and proposes a novel technique, "Malicious Off-chip Leakage Enabled by Side-channels" (MOLES), which employs power side-channels to convey secret information off-chip. An experimental MOLES circuit is designed with fewer than 50 gates and is embedded into an Advanced Encryption Standard (AES) cryptographic circuit in a predictive 45nm CMOS technology model. Engineered by a spread-spectrum technique, the MOLES technique is capable of leaking multi-bit information below the noise power level of the host IC to evade evaluators' detections. In addition, a generalized methodology for a class of MOLES circuits and design verification by statistical correlation analysis are presented. The goal of this work is to demonstrate the potential threats of MOLES on embedded system security. Nevertheless, MOLES could be constructively used for hardware authentication, fingerprinting and IP protection.

Since the vulnerability of cryptosystems to differential power analysis (DPA) was reported in 1999, various power analysis attacks and corresponding countermeasures have been studied. With the scaling down of supply voltage and CMOS technology below 90 nm, leakage power plays an increasing role in the overall power dissipation. Future cryptosystems need to address this trend, though it has not been of concern yet in low- cost cryptosystems such as smartcards and RFED tags which currently use older technologies and low performance transistors. In this paper, we explore the impact of leakage power on conventional DPA and the feasibility of a novel leakage-based DPA (LDPA). We first use SPICE simulations to explore the leakage dependence on input patterns of logic gates implemented in 90 nm, 65 nm, and 45 nm CMOS technologies. Then we simulate a successful LDPA on a subset of a DES cryptosystem with only 120 rounds, in contrast to the 200 rounds reported for a conventional DPA in 180 nm technology. Furthermore, we demonstrate how even a DES implementation using a DPA-resistant logic style can be broken with LDPA in 2000 rounds, compared with the conventional DPA using more than 5000 rounds.

This work examines a transmission system which adapts a finite set of code rates and a continuously varying transmit power. We propose a technique for finding the average reliable throughput (ART)-maximizing policy satisfying an average power constraint for a slow fading additive white Gaussian noise (AWGN) channel. ART is a measure motivated by the information outage and can, for example, be argued to characterize the long-term average throughput of a data packet transmission system with a transmit queue and a feedback protocol which requests retransmission of erroneously received packets. Given the size of the code rate set L, the ART-maximizing policy has the following properties. 1. For a given set of code rates, the optimum allocation policy suggests quantizing the fading state space into a set of L+1 corresponding intervals. For each quantization interval the optimal policy specifies a minimum transmitted power assignment which guarantees zero information outage. The optimum average power assignments across quantization intervals have a waterfilling relationship with respect to the interval channel quality measure. 2. The joint optimization of quantization intervals and the corresponding rate assignments are shown to have multiple local maxima. Nevertheless, this optimization problem can be reduced to a simple one-dimensional search over a parameter which determines the outage interval. Numerical results show that, in a Rayleigh-fading channel, there is only a 1-dB gap between the ergodic capacity and the throughput of a two-rate adaptive transmission system when the throughput is less than 6 bits/s/Hz. A special case of our optimal policy assignment is the optimal power and rate policy for an adaptive M-QAM system.

Without perfect channel state information at the transmitter, it is possible for adaptive transmission systems to experience information outage. In this paper, we formulate the throughput maximization with both an average power constraint and an information outage constraint. It is verified that, for the optimal transmission policy, the transmission only needs to adapt to a sufficient statistic for the channel state. For a Rayleigh fading channel with a simple training scheme, numerical results show that, with a reasonable amount of training and a small set of code rates, the adaptive transmission can achieve a performance very close to the ergodic capacity.

Throughput maximization of an adaptive transmission system with a finite number of transmission power levels and code rates for communication over slow fading channels is analyzed, based on the concept of information outage. Properties of throughput maximizing policies lead to an iterative algorithm that yields good system designs. Numerical results show that carefully designed discrete adaptive transmission systems with a small number of power levels and code rates can achieve throughput values close to ergodic capacity.

This article combines the concepts of ergodic capacity and capacity versus outage for fading channels, and explores variable-rate transmissions under a service outage constraint in a block flat-fading channel model. A service outage occurs when the transmission rate is below a given basic rate. We solve the problem of maximizing the expected rate subject to the average power constraint and the service outage probability constraint. When the problem is feasible, the optimum power policy is shown to be a combination of water filling and channel inversion allocation, where the outage occurs at a set of channel states below a certain threshold. The service outage approach resolves the conflicting objectives of high average rate and low outage probability.

This work examines an adaptive transmission system that supports a discrete set of code rates and continuously variable transmit power. Based on the concept of information outage, we maximize the system throughput over a slow fading channel. Properties of the throughput maximizing policies result in an iterative algorithm that yields good system designs. Numerical results show that in a Rayleigh fading channel, there is only a gap of 1 dB between the ergodic capacity and the throughput of a 2-rate adaptive transmission system when the throughput is less than 4 bits/sec/Hz.

In this work, we address optimal adaptive transmission policies in slow varying wireless environments. Continuous rate and power assignments that achieve the ergodic capacity for these channels have been derived previously. Nevertheless, from a practical point of view, use of a finite number of power and rate levels is imperative. Here, we address the mapping from channel states of an arbitrary distribution to a discrete set of power level and code rate pairs. Unlike earlier work, our design does not require that the transmitter knows the exact value of the current channel state. We show that our design yields results close to the well-known water-filling result.

In this paper, we study joint channel estimation and maximum likelihood decoding method for coded orthogonal frequency division multiplexing (COFDM) systems. Using this method in conjunction with convolutional coding, robust and nearly optimal coherent detection can be achieved in rapid dispersive fading channels. Significant performance gain in packet data throughput is realized in a system with aggressive frequency reuse.

We present physical and MAC layer techniques for high-speed wireless access to the Internet based on OFDM. Using dynamic packet assignment (DPA) for interference avoidance based on two examples of resource definition with different time and frequency units, we demonstrate that OFDM has significant flexibility to provide high transmission rates on demand with different available bandwidths. Innovations in radio link design, such as joint channel estimation and maximum likelihood decoding as well as interference suppression can be readily applied to coded OFDM systems. Significant performance gain in packet data throughput is realized in a system with aggressive frequency reuse.

In this paper, we propose two modifications to soft output Viterbi algorithm (SOVA) for turbo code decoding. One is to limit the reliability values to a small range to compensate for the defect brought by overestimating those values in the original SOVA. The other is to employ a new block interleaver to combat the tail effect of SOVA-based turbo code decoding. The simulation results show that the new SOVA with both modifications is able to obtain a similar result to that achieved by a maximum a posteriori (MAPI) algorithm with a random interleaver. In this paper, we also provide the results of the SOVA with the Battail's updating rule and compare them to those of the SOVA with the updating rule proposed by Hagenauer.