In this paper a new and simple method for 2-bit error correction for cross parity codes is proposed. All single and double bit errors, concerning data bits, are corrected. For checkbit errors up to a weight of 2, this method ensures that the data bits are free of errors. In a cross parity code the data bits are conceptually arranged in a rectangular array. The check sums are formed over bits along columns, rows and diagonals. In addition, the parity of all data bits is determined. If a 1-bit error occurs in the data bits, the erroneous bit is located at the intersection of three straight lines: a row, a column and a diagonal. For 2-bit data errors on distinct lines, the erroneous bits are located in the same way. For 2-bit data errors, that share a line, two straight lines per erroneous bit can be identified by the check bits. In a first step the bits at the four intersection points are inverted. Thereby the two errors are corrected and two new errors are generated. In case of odd side length, the two generated errors are located at three different straight lines each and can be easily corrected in a second step.

In this paper a new double-error-correction and triple-error-detection code as a modified BCH code is proposed. It is demonstrated by simulation experiments that the time delay for error correction of 2-bit errors is smaller for the proposed code as for a traditional BCH code with the same number of check bits and the same code distance 6. The new code is of interest for 2-bit error correction for memories.

In this paper a new 3-bit burst-error correcting code is proposed. Compared to a 1-bit error correcting Hamming code only two additional check bits are needed and compared to a 3-bit burst-error correcting Burton code the number of check bits can be reduced by 2. Since the proposed code is systematically designed by use of finite field algebra the code can be determined for an arbitrary word length and decoding is simple. Examples for different word length with up to about 1000 bits are described. The proposed code can correct single bit errors, adjacent two-bit errors, adjacent 3-bit errors and nearly adjacent 2-bit errors and may be useful for error correction in registers or register arrays, in combinational circuits and also in memories for which data-multiplexing is not used.

Imai-Kamiyanagi codes are a class of linear double error correcting (DEC) codes suitable for fast parallel error correction. The parity-check matrix H' of these codes is composed of submatrices based on BCH codes of small codeword length. To reduce the complexity of the decoder, the embedded BCH codes are used for error correction. To improve the applicability of Imai-Kamiyanagi codes, in this paper it is shown how triple error detection can be efficiently implemented using the small subsyndromes determined by the submatrices of H'.

In this paper we propose a modification of double error correcting (DEC) BCH codes that allows for a fast correction of arbitrary 1-bit and 2-bit errors, as well as 3-bit errors comprising adjacent 2-bit errors in certain bit positions. The proposed code has the same number of check bits as a double error correcting, triple error detecting (DEC-TED) BCH code with code distance 6. The proposed code is particularly useful for multi-level memories capable of storing more than one bit of data per memory cell. A method for decoding and a parallel implementation of the codes is described. Experimentally the decoding latency and area consumption is compared to parallel implementations of Hsiao SEC-DED codes, DEC BCH codes and TEC BCH codes for data bit sizes ranging from 8 to 1024 bits commonly used in memory applications.

This paper proposes the improvement of the method for soft error correction in the combinational circuit part of sequential circuits as described in [1], for which fault-tolerant master-slave elements are used. The errors in the combinational circuit part are detected by an error detection circuit and the error signal blocks the clock signal as long as the error exists. The system remains in its previous correct state and no complex recovery of the system is needed. In this paper we show how the method can be modified in such a way that it can be integrated into the standard industrial design flow and we demonstrate how the method can be favourably applied to a pipeline with different stages. Experimentally it is shown that the number of corrected errors can be increased by a factor of 4.22.

In this paper a simple method for fault tolerance with respect to transient or soft errors in the combinational part of sequential circuits is investigated. The memory elements of the sequential circuits are fault-tolerant master-slave-flip-flops. For correcting errors in the combinational part instead of error-correcting codes (ECCs) much simpler error-detecting codes can be used. An error detection signal indicating an error in a combinational part of the circuit blocks the clock signal in the second half of the clock cycle with the result that the previous correct state values of all the slave latches are preserved as long as the transient error (of any duration) stays in the combinational circuit. As soon as the transient error disappears, the system can continue to work from a correct state immediately; no complicated restart of the system is necessary. The system has only to stop for the duration of the transient error. The necessary time delay of the error signal determined by the error-detecting code limits the length of the clock cycle for which the proposed method is applicable. Therefore simple error-detecting codes such as parity codes, split-parity codes and duplication codes should be used. For the mentioned codes the time delay and the error detection probabilities which correspond to the error correction probabilities of this method are determined for benchmark circuits experimentally.

In this paper it is shown how the method of error correction of transient errors in a combinational circuit by use of error detection codes can be implemented for a sum-bit duplicated adder, thereby the outputs of the adder circuit are stored in fault-tolerant memory elements which are supposed to be fault-tolerant master-slave flip-flops. The combinational sum- bit duplicated adder circuit is monitored by an online detection circuit based on both a parity code and a duplication code. The error detection signal indicating an error in the combinational adder circuit blocks the slave clock signal in the second half of the clock cycle. The previous correct state values of all the slave latches are preserved for the duration of the transient error. As soon as the transient error disappears, the system can continue to work from a correct state, and no complicated restart of the system is necessary.

This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.

Circuits implementing the concept of Selective Fault Tolerance according to are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. This is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.

This paper introduces the concept of Selective Fault Tolerance for sequential circuits. A sequential circuit that is designed according to this method is fault-tolerant for an arbitrarily selected subset of input sequences that are applied in one or more arbitrarily specified states. Once a selected input sequence is applied in a specified state, the circuit guarantees the same degree of fault tolerance as Triple Modular Redundancy (TMR). No fault tolerance is guaranteed in any other case. A simple heuristic algorithm for the design of such circuits is presented and for a benchmark circuit the reduction of area overhead compared to TMR is experimentally determined. The proposed method is a generalization of Selective Fault Tolerance for combinational circuits as described in [1].

We present a new compactor architecture for extreme compaction of test responses with a high percentage of x-values. The test response data is compacted into a single, 1-bit wide bit stream. A major contribution of this work is a new technique to efficiently load x-masking data into a masking logic. A method eliminating the need for explicit mask control signals using ATE timing flexibility is also introduced. The proposed compactor can efficiently be employed in multi-chip testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.

This paper presents a new method of fault-tolerant design for combinational circuits. For an arbitrary chosen subset X1of inputs the designed system is fault-tolerant, but not necessarily for the other inputs. For all the inputs from X1the same level of fault tolerance as for Triple Modular Redundancy (TMR) is achieved. Compared to TMR the necessary area can be significantly reduced. Since the subset X1of inputs, for which the system is fault-tolerant, can be chosen by the designer, the proposed fault-tolerant design method is optimally adapted to the real requirements of fault tolerance.

This paper reports the experience being made during the implementation of low pin count techniques and their insertion into a production environment. The techniques applied are "on-loadboard compare" and "shared driver". Already known on a concept level for an on-chip approach, in this paper the transfer to an on-loadboard solution is presented. Emphasis is put on production related aspects. Practical experience, challenges, and pitfalls are described to allow a better assessment of risks and benefits of the investigated methods.

In this paper we consider the test of large circuits. Due to the increasing number of scan chains of industrial designs and due to the limited recourses of the ATE-equipment the compression ratio of the test responses increases. A second issue are undefined states (X-values). In the presence of X-values during test a considerable number of the scan cells cannot be observed at the compressed outputs. We present a new hierarchical two-step method of X-masking to achieve a high observability of scan cells and to reduce the overhead for X-masking. For every scan-shift cycle the generated X-mask is either set to be active or not. By this method the number of X-values at the compacted outputs is considerably reduced. The remaining small number of X-values can be tolerated by an X-tolerant compactor. To implement this method a hierarchically configurable register is used.

In this paper the design of error detection circuits for split-parity codes is investigated. In a split-parity code the linear parity bit is split into two nonlinear check bits. Split-parity codes, like parity codes, detect all odd errors with certainty; all even errors - which remain undetected by parity - are detected with a probability of 50%. It is shown that a large variety of split-parity codes exist which can be utilized for the optimization of error detection circuits with respect to area and error detection probability. It is demonstrated that split-parity codes are a cost-effective possibility to design error detection circuits.

In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern automatic test equipment (ATE). In our design the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are driven by a clock which is k times faster than the slower test clock of the scan chains. For each test clock cycle only one out of the k different outputs of each shift register is evaluated by the ATE. To mitigate the negative effects of consecutive X values within the scan chains, a permutation of the NF-MISR inputs is periodically applied. Thus, no additional external control signals or test set dependent control logic is required. The possibilities of an implementation on a Verigy ATE will be described. The presented results for three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial ATPG tool.

This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrection for the widely used class of odd-weight column codes is derived and actual codes which are very close to that theoretical bound are presented. Surprisingly, significantly better results are obtained with shortened generalized Hamming codes. An optimal (39,32)-SEC-DED code with 32 information bits and 7 control bits is determined which has the lowest risk of triple bit miscorrection of any possible linear (39,32)-code. It is shown how codes with 64 and 128 information bits with significantly lower triple bit miscorrection probability than currently used codes can be derived from that code.The new codes also feature adjacent double bit error correction capabilities (SEC-DED-DAEC codes). Employing them in a SEC-DED-DAEC checker reduces the risk of miscorrecting non-adjacent double bit errors by 27-34% compared to the best codes known.

This paper introduces the concept of utilizing the timing flexibility of automatic test equipment (ATE) when designing X-tolerant test compactors. Redundant information is generated by the compactor and transferred to the ATE at a frequency k times higher than the scan shift frequency. This technique is different than current X-tolerant compactors where the necessary redundant information is generated on additional compactor outputs. If the Compactor design can take into account the ATE capabilities, the knowledge of the redundancy can be efficiently used. The ATE will select the relevant information out of the compacted test response, which then leads to a reduction of the ATE compare data by a factor k. In the best case this method can be applied without extra costs related to the higher frequency. The benefit of this approach is a higher parallel test factor due to the reduced number of output pins. This paper explains the capabilities of the employed ATE which need to be taken into account when designing an X-tolerant compactor using a higher output data rate. The method is also demonstrated on a shift register which works at a multiple of the scan shift frequency.

We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theory of output deviations, can be used to supplement tests for classical fault models, thereby increasing test quality and reducing the probability of test escape. Output deviations can also be used for test selection, whereby the most effective test patterns can be selected from large test sets during time-constrained and high-volume production testing. Experimental results are presented to evaluate the effectiveness of patterns with high output deviations for the single stuck-at and bridging fault models

Technology and product ramp up suffers increasingly from systematic production defects. Diagnosis of scan test fail data plays an important role in yield enhancement as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production can lead to significant test time overhead. This paper presents a new on-chip architecture that evaluates scan test results and stores relevant scan diagnosis information on chip. Scan diagnosis data can be accessed after the scan test has finished with very little test time overhead. Moreover, the proposed technique is ATE independent. An implementation example, based on a state-of-the-art SoC device, is reported

In this paper a new code-disjoint self-checking non-restoring array divider is proposed. The divider array which is designed by use of different carry-dependent sum-adder cells is parity checked. Only a single carry-out signal per adder cell is needed. Both the output registers for the dividend and for the remainder are (inverted) duplicated to guarantee a high coverage for soft errors. For the first time also the final correction adder is concurrently checked. Non-restoring array dividers for 8-bit, 16-bit and 32-bit dividends are designed by use of the SYNOPSYS tools by EUROPRACTICE. Compared to a non-restoring array divider without error detection the area overhead is about 30 % and the additional delay is only from 2% to 11 %

In this paper, a new self-checking code-disjoint Booth-2 multiplier with an improved error detection and with a reduced area overhead is proposed. Compared to the 64 times 64 multiplier without error detection the area for the proposed multiplier increases for the different implementations only by 23%-30%. Especially for soft errors the error detection capability is significantly improved. All even or odd (soft) errors in the output registers are detected

In this paper we experimentally investigate the efficiency of concurrent checking for the AES encryption algorithm (Rijndael) by parity modification according to K. Wu et al. (2004). Also we propose a simple BIST method. For BIST the implementation of the AES algorithm itself is used as well as a pseudo-random test input generator and a compactor of the test results. Thereby we utilized the property of the AES algorithm that arbitrarily given plain texts are encrypted by the successive rounds into "pseudo-random" cipher texts which are the (test) inputs for the next round. The complete data path of the AES algorithm is simulated as a netlist of AND-, NAND-, OR-, NOR- and XOR-gates. All possible single stuck-at faults are injected and simulated. For a special implementation of the S-boxes all errors within the data path of the AES algorithm due to single stuck-at faults are immediately detected.

In this paper a new diagnosis method for scan designs with many scan-paths based on error correcting linear block codes with N information bits and K control bits is proposed, where N is the number of scan-paths. The new approach can be implemented on a modified STUMPS-architecture. In diagnosis mode the test has K times to be repeated. In the K repetitions of the test the outputs of the scan-paths are connected to a configurable signature register (with disconnected feedback logic) according to the coefficients of the K syndrome equations of the code. By monitoring the one-dimensional output sequence of the configurable signature register the failing scan-cells in the different scan-paths can be identified with the resolution of the selected error correcting code. Since for the relevant codes, e.g. (shortened) Hamming codes, T-error correcting BCH-code, the ratio K/N decreases very fast with an increasing number N the method is useful for a large number of scan-paths.

In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. For 64 bits area and maximal delay are determined by the SYNOPSYS CAD tool of the EUROCHIP project. Compared to a 64 bit carry-select adder without error detection the delay of the most significant sum-bit does not increase. The area is 170% of a 64 bit carry-select adder (without error detection and not code-disjoint).

In this paper a new self-checking multiplier which consists of an AND-matrix, a carry-save adder and a final sumbit duplicated adder is proposed. The AND-matrix and the carry-save adder are parity checked. All errors due to single stuck-at faults in the combinational part and all even or odd (soft) errors in one of the duplicated output registers are detected. The parity checked carry-save adder is implemented by use of carry-dependent sum adder cells with a single carry-out signal. Compared to a corresponding multiplier without error detection the necessary area is about 125% to 135%.

We present a new low-cost concurrent checking method for the advanced encryption standard (AES) encryption algorithm. In this method, the parity of the 128-bit input is determined and modified step-by-step into the parity of the 128-bit output according to the processing steps of the AES encryption. For the parity-preserving AES steps shift-rows and mix-column no parity modifications are necessary. The modified parity is compared in any round with the actual parity of the outputs of the round. To obtain the hardware costs we implemented this method on a Xilinx Virtex 1000 FPGA. For this implementation, the hardware overhead is about 8% and the additional time delay is about 5%. The method detects technical faults and deliberately injected faults during normal operation.

A methodology for the synthesis of partially self-checking multilevel logic circuits with low-cost parity-based concurrent error detection (CED) is described. A subset of the inputs of the circuit is selected to realize a simple characteristic function such that CED is disabled whenever the inputs belong to the OFF-set of the characteristic function. This don't-care space in the operation of the CED circuitry is used to optimize the CED circuitry during synthesis. It is shown that this methodology is very effective at targeting faults with a high sensitization probability. Experimental results show that the proposed approach, which is of special interest in applications where a low-cost CED solution is desired, achieves a significant reduction in the error rate in logic circuits.

In this paper a new self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks.

Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption. We will describe a general concurrent error detection (CEO) approach against such attacks on symmetric block ciphers using CS-cipher as an example. The proposed CED compares a carefully modified parity of the input plain text with that of the output cipher text. An analysis of the CS-Cipher shows that on one hand the parity of its inputs is modijied by a constant one or zero by component-wise exclusive-or of inputs with the round keys and with the round constants; if the parity of the round keys and of the round constants is odd (even) the parity of the inputs is mod$ed by one (not modijied). On the other hand, the diffusion network based on the Fast Fourier Transform does not alter the parity. Finally, the 16-bit to 16-bit non-linear mixing function does not have any simple relation between the parity of its inputs and of its outputs. The mixing function is composed of a linear function q and a non-linear function p. In order to maintain the invariance of the parity from the inputs to the outputs of each CS-cipher encryption round, we added a parity correction term (exclusive-or of the parity of its inputs and outputs) to the non-linear function p and slightb modijied the parity function due to the linear function p Faults introduced into the CS-cipher design are detected by comparing the overall parity of the input mod$ed by the parity of the round keys, round constants and correction terms of the mixing functions with the parity of the (intermediate) cipher text obtained ajer every step of an encryption round.

A structure-independent method for space compaction in combinational circuits based on a new generic scheme is presented. It is shown that a single-output compactor can always be designed for compressing test responses of a circuit-under-test (CUT) with guaranteed zero-aliasing. Test responses from multiple outputs are compacted to a single periodic data stream. The compactor is independent of the fault model and can be designed only from the knowledge of the given test set and the corresponding fault-free responses. An additional response logic and a special code checker are used to design the compactor. The same test set given for the CUT also detects all multiple stuck-at faults in the response logic and almost all faults in the rest of the compactor. Further, time compaction is also easily achieved. Since the design can be accomplished without any information about the structure and functionality of the CUT, it would be useful for testing embedded cores as their internal structures may not be transparent to the users.

Built-in self-test (BIST) is an attractive design-for-test methodology for core-based SoC design because of the minimal need for test access when tests are generated and evaluated within the core itself. However, the scan based logic BIST approach being widely considered for this application suffers from two significant weaknesses: slow test-per-scan execution, and a limited capability for detecting realistic timing and delay faults, critical in deep submicron technologies. The new multimode scan based approach presented here supports test-per-clock BIST, which runs orders of magnitude faster, and also provides significantly better delay fault coverage.

Presents the design of robust space compactors for reducing test data volume. These compactors are totally error-propagating for a given test test set, i.e. all possible errors are propagated irrespective of the fault model. In addition, these compactors also provide a high degree of error propagation for other test sets. All errors that affect up to three outputs of the circuit under test, as well as all errors that affect an odd number of outputs, are detected. This is irrespective of the test set or the fault model. The number of compactor outputs grows very slowly with the number of circuit outputs and size of the test set. Finally, no structural information of the circuit under test is required for fault simulation. We present experimental results on compactor design for a set of ISCAS and ITC-99 benchmark circuits.

We present a new scan-BIST approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of test vectors to the circuit under test. Two MISRs (multiple-input signature registers) are used in an interleaved fashion to generate intermediate signatures, thereby obviating the need for multiple test sessions. The knowledge of failing and non-failing intervals is used to obtain a set S of candidate failing vectors that includes all the actual (true) failing vectors. We present analytical results to determine an appropriate interval length and the degree of overlap, an upper bound on the size of S, and a lower bound on the number of true failing vectors; the latter depends only on the knowledge of failing and non-failing intervals. Finally, we describe two pruning procedures that allow us to reduce the size of S, while retaining most true failing vectors in S. We present experimental results for the ISCAS 89 benchmark circuits to demonstrate the effectiveness of the proposed scan-BIST diagnosis approach.

In this paper a systematic scan-path design with duplicated and inverted duplicated memory elements is proposed. Contrary to a known solution (Raina et al., 2000), no additional control lines for additional multiplexors are needed. Full controllability and observability of the proposed scan-path is demonstrated.

This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. In a general circuit, compaction of output space to a single output with zero-aliasing cannot always be achieved by earlier known approaches. In this work, it is shown that given a precomputed test set T, the test responses at the functional outputs of any arbitrary circuit-under-test (CUT) can be compacted to a single periodic output, with guaranteed zero aliasing. All the errors that are produced by T at the outputs of the CUT will also appear at the output of the compactor. The method is independent of the fault model and the structure of the CUT and uses only the knowledge of the test set T and the corresponding fault-free responses. A new concept of distinguishing outputs and a characteristic function is used to design the compactor. The test vectors in T are appropriately ordered to optimize the compactor logic, which to achieve zero-aliasing uses a test pattern counter to designate the sequence of test application and a special code checker. A design procedure is described to synthesize the compactor using logic synthesis tools, and relevant experimental results on hardware overhead for several benchmark circuits are presented. It is further shown that the overhead can be significantly reduced if the constraint of exact zero aliasing is slightly relaxed.

This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. It is shown that given a precomputed test set T , the test responses at the functional outputs of the given circuit-under-test (CUT) can be compacted to a single periodic output, with guaranteed zero-aliasing. The method is independent of the fault model and the structure of the CUT, and uses only the knowledge of the test set T and the corresponding fault-free responses---it is particularly suitable for intellectual property (IP) cores. A new concept of distinguishing outputs and characteristic response function is utilized for synthesizing the compactor. Relevant experimental results on hardware overhead for several ISCAS circuits are presented. 1 Introduction Space compaction, which refers to the problem of reducing a wide data stream to a narrow signature stream, is commonly used for test response compression. Atypical space compaction scheme for a general c...

A new diagnosis method for combinational circuits is proposed which is a modification of traditional signature analysis. By this method, instead of a technical fault the first erroneous test response in the presence of the considered fault is determined. Additionally to the accumulated signature a one-dimensional output sequence of the MILFSR is monitored during test and diagnosis. Some of the test inputs have to be repeatedly applied for diagnosis.

A new code-disjoint self-checking carry look-ahead adder is proposed. To reduce the necessary area and the power dissipation only the sum bits of the adder cells are duplicated. This is possible since the input parity is determined by use of internal nodes of the adder cells. The adder is modeled by a SYNOPSIS CAD tool from the EUROCHIP-Project with a standard library. With respect to duplication and comparison the necessary area and the power dissipation can be reduced up to 38 % and up to 29 % respectively compared to an increase of the maximal delay of only 12 %.

We present an efficient space compaction method which propagates all realistic errors that can appear at the outputs of a circuit under test in response to a precomputed test set. Since the proposed method does not rely on structural information of the circuit under test, it can be readily applied to intellectual property (IP) cores. Space compaction of test responses for IP cores provides parallel access to their functional outputs and reduces testing time. A /spl delta/-bounded-weight error model is combined with a /spl delta/-response graph model to generate the logic specification for the compactor via graph coloring. Moreover, a carefully-chosen subset of inputs of the circuit under test allows error propagation to be achieved using an arbitrarily small number of compactor outputs. The error-bound variable /spl delta/ parametrizes the space compactor, and the synthesis approach can be used to design several space compactors for the same circuit under test by simply varying /spl delta/. We illustrate the proposed method by presenting experimental results on compactor synthesis for several large ISCAS benchmark circuits.

In this paper we propose a new method for the design of duplex fault-tolerant systems with early error detection and high availability. All the scannable memory elements (flip-flops) of the duplicated system are implemented as multimode memory elements according to Singh et al. (1999), thus allowing during normal operation the accumulation of a signature of its states in its scan-paths. By continuously comparing a 1-bit sequence of the compacted scan-out outputs of the accumulated signatures of the duplicated systems an error can be already detected and a recovery procedure started before an erroneous result appears at the system outputs when a computations is completed. The accumulation of a signature during normal operation can also be used for debugging at-speed. For this application the system need not be duplicated.

The Multi-Mode Scannable Memory Element (MSME) is a design-for-test technique that combines the testing efficiency of the Circular Self-Test Path approach with a full scan capability to support custom test vectors, diagnosis, and design debugging. A key feature is the ability to support pseudorandom at-speed delay testing of the functional circuit paths without imposing any performance penalty on the design beyond that for traditional scan. This paper presents a CMOS design for the MSME, and investigates benchmark circuits designed with this memory element. The results show that very high stuck-at and transition delay test coverage can be achieved for most cases using the pseudorandom self-test mode alone. Evaluation of layouts indicates low to moderate area overhead.

In this paper a new totally error propagating compactor is proposed which can be used for arbitrary core-based designs and also for mixed signal ICs with digital interfaces. All errors at the outputs of the cores are detected at the outputs of the proposed compactor. This property is achieved with a small amount of time redundancy.

In this paper we propose a new method for the implementation of a self-dual circuit with alternating inputs. For every circuit output the self-dual complement is designed. Contrary to ordinary duplication and comparison the corresponding self-dual complements and the monitored circuit itself can be jointly, implemented. The self-dual duplicated circuits can be used in test mode, online mode and in fast mode without alternating inputs. Because of the necessary time redundancy, the approach is especially useful for online testing of control systems for which time is not critical.

In this paper, a new compaction technique based on signature analysis is presented. Rather than comparing the final signature with the expected one after the test is completed, the binary output of the MISA is converted into an alternating binary signal by two simple cover circuits. An error is indicated whenever the alternation of the output signal is disturbed. This technique results in a higher fault coverage, improved fault diagnosis capability, a greater test autonomy in core-based designs, and early fault notification.

In this paper a new structural method for linear output space compaction is presented. The method is applicable to concurrent checking and built-in self test (BIST). Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs output partitions are determined without fault simulation. For all ISCAS 85 benchmark circuits three groups of compacted outputs are sufficient to achieve 100% fault coverage in test mode and for 3 to 5 groups an error detection probability of 98% is obtained in on-line mode. The method can be applied to very large circuits.

This paper introduces a new multimode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the need of any design changes. As in the case of scan, the new element is used in place of regular flip-flops in the design library. Interconnect overhead is comparable to scan with reset. Concurrent with normal operation, the design accumulates a signature of the state variables in the scan-register configured as a multiple input signature analyzer (MISA). Thus virtually complete state observability is achieved without the need of scanning-out the state for each test-input. The pseudorandom states of the MISA can also be utilized as state inputs in circular testing. In this way, most faults are covered in a pseudorandom, "test per clock" mode. Only a few random pattern resistant faults require scan, greatly reducing test application time. Pseudorandom delay testing of the true normally active circuit paths is also possible. Two-pattern tests are supported. Finally, we show that the new memory element can also be used for fault-tolerant design.

In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into two different types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities.

In this paper for an arbitrary linear separable code the concept of a COde Preserving Multi-Input Signature Register COPMISR is introduced. For a code with k control bits 2/sup k2/ different COPMISR's can be designed. The optimum COPMISR with a minimum number of XOR-gates can be chosen from this large set. By different examples it is shown how the newly introduced COPMISR can be simultaneously utilized for concurrent checking, testing and localization of an eventually erroneous component of the monitored system. Since parity codes, group-parity codes, duplication codes and Hamming codes are special linear separable codes the concept of the COPMISR has a wide range of applications in different areas of on-line error detection and BIST.

Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper. This method is based on the newly introduced concept of a self-dual complement of a given Boolean function. The parity prediction function f/sub p/ of ordinary parity checking is replaced by the self-dual complement /spl delta//sub p/ of this function such that the module-2 sum of the outputs of the monitored circuit and of /spl delta//sub p/ is an arbitrary self-dual Boolean function h. Because of the large number of possible choices for h as an arbitrary self-dual Boolean function, the area overhead for an optimal self-dual complement /spl delta//sub p/ is small. Alternating inputs are applied to the circuit; the output h is alternating as long as no error occurs. The fault coverage of this method is almost the same as for parity checking. The usefulness of the proposed method is demonstrated for MCNC benchmark circuits.

In this paper it is shown how a self-checking checker can be designed to monitor systems with very few encoded outputs which are code words of an arbitrary separable error detection code. The checker is completely tested in normal operation mode, independent of the number of code words which are to be monitored. If an error has been indicated in normal operation mode the erroneous component of the system can be identified in test mode by the same hardware. A linear feedback shift register (LFSR) is included between the information bits of the outputs of the monitored systems and the inputs of the check-bit generator. A corrector (Cor) adjusts the check bits of the monitored system. The general systematic design method given in this paper is applied to parity codes, duplication codes, arithmetic codes and Berger codes. The approach is useful for the design of ultra-reliable fault-tolerant systems, especially for monitoring systems with very few outputs in normal operation mode.

In this paper we propose a new self-checking comparator with one periodic output. The comparator can be used as a two-rail checker or as an equality checker. Two different input patterns are sufficient to detect all the faults considered.

No abstract available.

In this paper it is shown how an arbitrary n-tupel of m-ary Boolean functions can be systematically implemented as a code-disjoint self-testing combinational circuit. This is achieved by the use of a parity bit of the inputs and a parity bit of the outputs, a second additional output and of one or more replicates of a selected part of the monitored circuit. The parity bit of the outputs and the functional bits are thus jointly designed rather than in separation. The circuit can be used in test mode, in scan-test mode if it is the combinational part of a sequential circuit, and in normal operation mode for concurrent fault detection. In normal on-line operation, faults may be detected with some degree of latency.>

In this paper we propose a structure dependent method for the systematic design of self--checking error detection circuits wich is well adapted to the technical fault model considered. For online detection, the hardware is in normal operation mode, and for testing in test mode. In the test mode, these error detection circuits guarantee a 100\\% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults.

A method of compiler generated checkpoints for the detection of permanent hardware faults is offered. Some of the floating point addition instructions of a program are used as checkpoints. The compiler automatically generates a diverse execution on different data paths (pseudo-duplication). Rounding-modes and fault coverage are investigated. The method can be implemented without additional hardware and with a tolerable reduction in performance.>