In this paper a new VCO-based MASH delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization error of the first stage as a pulse signal that is applied to the second stage. Based on the architecture, the input of the first VCO is a very small signal and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power hungry linearization methods. Behavioral-model simulations show a 70 dB SNDR improvement from a standalone open loop VCO-based ADC in the presence of nonlinearity.

Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL convention logic (NCL) and traditional clocked Boolean logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 μm process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta-sigma modulator (DSM) example. The signal-to-noise ratio performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency.

This paper presents a technique for automated design and optimization of low-noise oscillators. A sensitivity analysis for oscillators guides the reduction of oscillator noise intensities and improvement of oscillator's immunity to noise. A design-oriented approach to circuit analysis efficiently handles design constraints and reduces the dimensionality of the optimization problem. The perturbation projection vector based phase noise computation makes the proposed optimization technique general and applicable to all types of oscillators, independent of circuit topology. Several examples illustrate the benefits of the new optimization approach.

A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performance specified by a set of equality constraints. This is done by including the design equality constraints and the circuit parameters directly in the steady-state analysis as additional equations and unknowns. A time-domain finite difference method and the numerical implementation for the proposed analysis are described. Several examples demonstrate that the new analysis accurately and efficiently tunes circuit parameters that conform to a wide range of design specifications.

A new oscillator sensitivity analysis that predicts the impact of parameter variations of a VCO in a PLL is presented in this paper. Sensitivities of an oscillator's steady-state performance to design, process, or environmental parameter variations can be accurately and efficiently computed with the proposed analysis.

This paper presents an analysis for calculating sensitivities of an oscillator's periodic steady state and perturbation projection vector to design, process, or environmental parameters. A general continuous-time formulation and time-domain numerical methods are described. The applications of the oscillator sensitivity analysis in design optimization, macromodeling, as well as in analyzing the impact of process variations are demonstrated through examples.

A new green function-based method for extracting parasitics in inhomogeneous substrates is presented. This approach overcomes the limitation of prior green function-based methods and allows extraction of substrate parasitics in the presence of sinkers, trenches, and wells. A careful use of volume and boundary-element meshing, as well as discrete transforms, yields a technique that is computationally efficient. The accuracy of the method is comparable to that of 3-D semiconductor device simulators with significantly smaller computational costs.

This paper presents a generalized formulation of the periodic steady-state analysis for oscillators. The new formulation finds the value of a circuit parameter that results in a desired oscillation frequency for the circuit. Numerical methods based on the time-domain finite difference and shooting methods, and the frequency-domain harmonic balance method are described. Comparisons with search-based methods demonstrate the efficacy of the new approach.

This paper presents an analysis for calculating sensitivities of an oscillator’s periodic steady-state and perturbation projection vector to design, process, or environmental parameters. A general continuous- time formulation is described. Applications of the oscillator sensitivity analysis in design optimization and macromodeling are demonstrated through examples.

Key issues in wireless receivers for wireless sensor networks are discussed and existing implementations are compared. On the system level, a new method to determine power allocation is developed to ensure system requirements are met while minimizing power consumption. On the circuit level, several common designs are reevaluated in the context of low power design and the best choices for low power CMOS receiver design are given. A noise analysis shows that for extremely low power operation, the common gate LNA provides better noise performance over the commonly used common source design. Existing filters are compared and a figure of merit is used to determine the best architecture for low power design. Circuit simulations are used to show that a higher power limiting amplifier can reduce the overall receiver power for a given set of noise and gain specifications.

A new super-regenerative transceiver for use in low power binary frequency shift keying (BFSK) digital communication systems is presented. The classic on/off keying (OOK) design is reviewed and motivation to extend the design to BFSK is given. The system is shown to preserve the low power qualities of the classic super-regenerative transceiver while obtaining the increased speed and reliability of BFSK modulation. Operation of the new system is explained at the system level and insight into the circuit design is also given. Simulations show the transceiver allows transmission rates on the order of 250kbps with a link power of less than 1.4mW.

A fully integrated 4.2GHz single-ended Clapp VCO is presented in 0.25μm CMOS technology. The PMOS-based VCO is voltage biased using an inductor to achieve higher swing and better phase noise. With an inductor Q of only 6.5, the VCO achieves a phase noise of -143.5dBc/Hz at 3MHz offset, resulting in a figure of merit of -188.9dBc/Hz.

This paper presents an analysis to model the Brownian motion induced noise in MEMS varactor based RF VCOs. A noise current model is used to describe the upconversion mechanism of Brownian noise. How this model lends itself to the computation of phase noise using a nonlinear perturbation technique was shown. A behavioral model to describe the noise characteristics of MEMS varactors is also presented.

In this paper a modification of the time-domain periodic steady-state analysis for oscillators is presented. The proposed analysis finds the value of a circuit parameter that results in the circuit oscillating at a desired frequency. This analysis is based on the steady-state analysis for voltage and current controlled oscillators, i.e., replacing the oscillation period by a circuit parameter in the list of unknowns. A generalized formulation that can handle a control voltage or current, as well as any frequency-tuning circuit parameter, such as a tank capacitor or device geometry is developed in this paper.

The loop dynamics of a radio-frequency (RF) micro-electromechanical system (MEMS) based charge-pump phase-locked loop (CPLL) have been investigated using a continuous time analysis. This analysis reveals the bandwidth limitations of a PLL due to the MEMS varactor. A technique is presented to overcome the inherent low bandwidths by modifying the loop filter circuit. A 1.56GHz PLL is designed and simulated for a Global Positioning System (GPS) application using this technique

LC-tuned voltage controlled oscillators (LC VCOs) are widely used in high performance phase locked loops (PLLs) and frequency synthesizers due to their high spectral purity. The oscillation frequency of an LC VCO is commonly assumed to be the resonant frequency of the LC tank. However, this is not accurate as shown in this paper. The oscillation frequency is also affected by the bias current. By applying our analysis to the Hegazi and Abidi's LC VCO, we propose a new digital trimming technique which can compensate for process variations and improve the phase noise performance

A new multiple-probe method is presented for the simulation of highly nonlinear ring oscillators using the harmonic-balance method. This method is robust compared to the conventional single-probe method and readily converges for a wide range of single-ended and differential ring oscillators. Furthermore, it is computationally more efficient for ring oscillators in which the conventional single-probe method converges

The simulation of high-Q oscillators in the frequency domain is difficult due to a very small region of convergence. In this paper, globally convergent homotopy methods are combined with the harmonic balance method for simulation of high-Q oscillators. Various homotopy options have been evaluated, and an algorithm has been developed that is robust in simulating a wide range of oscillator circuits

This paper examines three algorithmic approaches for the frequency-domain harmonic-balance method in a coupled device and circuit simulator. These are the nonquasi-static, quasi-static, and modified Volterra series approaches. A detailed qualitative and quantitative comparison between these approaches is provided in terms of accuracy and the computational resources required

This paper presents an error control method for application of the discrete cosine transform (DCT) to extraction of substrate parasitics in integrated circuits. In addition to the truncation error with approximating an infinite series with a finite number of terms, there are also errors in approximating the truncated series by the DCT. It is shown that this error is important for accurate parasitic extraction and isolation calculation and can be controlled by applying an interpolation method. The interpolation method also makes it possible to use a smaller DCT size without loss of accuracy.

A novel approach for simulating the periodic steady state of ring oscillators with the harmonic balance method is described. A single delay cell based equivalent circuit is simulated and used to determine the response of the overall circuit. This results in an algorithm that is computationally efficient and readily converges for a variety of ring oscillator circuits.

This paper presents a new Green function-based approach for substrate parasitic extraction in substrates with inhomogeneous layers. This new formulation allows analysis of noise coupling with sinkers, trenches and wells, - a limitation in prior Green function-based extractors. Numerical examples for sinkers and trenches are provided and compared with the results from threedimensional semiconductor device simulations. It is shown that the proposed method is accurate and computationally efficient.

A novel approach for simulating the periodic steady state of ring oscillators with the harmonic-balance method is described. This approach is efficient and robust compared with traditional approaches. The key idea exploited is the structure of the ring oscillator, in which the properties of a single delay cell are used to simulate the response of the overall oscillator. The proposed method yields an algorithm that is computationally efficient and readily converges for a wide variety of single-ended and differential ring-oscillator circuits.

This paper presents an analysis of the numerical stability for the formulation of the Green's function method of Niknejad et al. (1998) for modeling and analysis of substrate coupling in integrated circuits. It is shown that the formulation has numerical overflow problems. A new stable formulation is presented.

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.

This paper presents an automated methodology for calibrating the doping profile and accurately predicting substrate parasitics with boundary element solvers. The technique requires fabrication of only a few test structures and results in an accurate three-layered approximation of a heavily doped epitaxial silicon substrate. Using this approximation, the extracted substrate resistances are accurate to within 10% of measurements. The calibrated parasitic extractor results in good agreement between simulations and measurements for substrate noise coupling in fabricated test circuits.

An algorithm for the robust and efficient simulation of high-Q oscillators using the harmonic balance method is presented. Globally convergent homotopy methods are combined with the harmonic balance method for high-Q oscillator simulation. Various homotopy options are evaluated leading to an algorithm that is applicable to a wide variety of oscillator circuits.

A scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. This model is simple since it requires only four parameters which can readily be extracted from a small number of device simulations or measurements. Once these parameters have been determined the model can be used for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated for a 2 /spl mu/m and a 0.5 /spl mu/m CMOS process where it is shown that the simple model predicts the noise coupling accurately. Measurements from a chip fabricated in a 0.5 /spl mu/m CMOS process show good agreement with the model.

For original paper see E. Abou-Allam and T. Manku, ibid., vol.16, pp.437-47 (1997). A comparison is provided between the recent small-signal analysis for the distributed gate resistance in MOSFET's at RF frequencies and the lumped-element model of an earlier publication for various CMOS technologies. An improved lumped-element model is also proposed. It is demonstrated that simplified lumped-element circuits are adequate for modeling the effect of distributed gate resistance on both the y parameters and the thermal noise.

An intelligent partial Gauss-Seidel scheme (PGS) for general circuit simulation is described. This approach is a novel combination of direct solution using incomplete LU factorization, and iterative solution using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Reliable analytic rules are derived such that terms that would be relaxed in Gauss-Seidel are relaxed only if they are considered small by applying these rules. Solution speeds up to ten times faster than direct methods have been demonstrated and higher gains are anticipated for larger circuits. This scheme is robust and accurate for circuits with many different element types, including bipolar transistors, MOSFETs, diodes, inductors, and dependent sources.>

Algorithms for transient mixed-level circuit and device simulation using a full two-carrier three-dimensional (3-D) device simulator SIERRA and the circuit simulator SPICE3 are presented. Circuit and device simulator coupling algorithms that are suited for two-dimensional mixed-level circuit and device simulation using direct solvers cannot be successfully employed when iterative solution techniques are used in 3-D device simulation. New algorithms to couple the circuit and 3-D device simulator have been developed and evaluated. The importance of 3-D mixed-level circuit and device simulation is demonstrated by applying it to single-event upset in CMOS SRAM cells.>

A general framework for mixed-level circuit and device simulation is described. This framework was used in the development of the simulation program CODECS (coupled device and circuit simulator). Various algorithms to couple the device and circuit simulators for DC and transient analyses have been implemented in CODECS. These algorithms are evaluated based on their convergence properties and run-time performance. This study provides guidelines for choosing a particular coupling algorithm. A modified two-level Newton algorithm is used for DC analysis, whereas a full block-LU decomposition algorithm is used for transient analysis. This combination of algorithms provides reasonable convergence and run-time performance. A simple latency scheme provides a 50% speedup. Coupling for small-signal AC and pole-zero analyses are described.>

The authors describe algorithms for transient mixed-level circuit and device simulation using a two-carrier three-dimensional device simulator SIERRA and the circuit simulator SPICE3. It is pointed out that algorithms well suited to 2D mixed-level circuit and device simulation cannot be successfully used. The memory and CPU time requirements in 3D device simulation necessitate it the use of iterative solution techniques at the device level, which impose an additional constraint in developing efficient algorithms. Two node tearing schemes are shown to be the most promising schemes for coupling the circuit and device simulators. An application of 3D mixed-level simulation to the study of single-event upset of SRAM cells is presented.>

The authors present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and bipolar junction transistor (BJT) circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a matrix partitioning scheme.>

Two techniques for general circuit simulation, an intelligent, partial Gauss-Seidel scheme (PGS) and a preconditioned conjugate-gradient scheme (PLUCGS), are described. Both techniques are robust and accurate for bipolar and MOS analog and digital circuits. PGS is a novel combination of direct solution, using LU factorization, and iterative solution, using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Solution speeds up to 6 times faster than direct methods have been demonstrated and higher grains are anticipated for larger circuits. The second method, PLUCGS, uses a partial LU factorization as a preconditioner; a vectorized implementation on a CONVEX C-240 computer is 5-7 times faster than the direct solution method with only one-fourth the memory requirements.>

Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration. CODECS is a mixed-level device and circuit simulator that has been developed to support a variety of numerical models and analyses capabilities. Effective coupling of device and circuit simulation capabilities is achieved by a proper choice of algorithms and architecture. Several examples illustrate the advantages of CODECS for simulating both MOS and bipolar circuits.>

The techniques described have been implemented in a multilayer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problems into two-layer and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2 (see ibid., vol.CAD-4, no.3, p.208-19, 1985). In particular, a three-dimensional maze router is used for the vertical connections; this methodology is effective even when cycle constraints are present. Chameleon has produced optimal results on a wide range of industrial and academic examples for a variety of layer and pitch combinations, and can handle a variety of technology constraints.>

New techniques for routing general multi-layer channels are introduced. These techniques can handle a variety of technology constraints. For example, linewidth and line-to-line spacing can be specified independently for each layer, and contact stacking can be allowed or forbidden. These techniques have been implemented in a new multi-layer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problem into two and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2. In particular a three-dimensional maze router is used which guarantees that any problem can be routed even when cyclic constraints are present. Chameleon produces optimal results on a wide range of industrial and academic examples for any number of layers and pitch combinations.