Fan proposed a set of hyperuniversal switch blocks (HUSBs), called Fan’s (4,${w}$)-HUSBs in this paper. He also proved that his design with${w}$less than 6 was optimum. That is, they used the least switches to achieve hyperuniversal routability. However, we find a counter example to show that there is an unnecessary switch in Fan’s (4, 4)-HUSB. Namely, we propose a new (4, 4)-HUSB, water-molecule-shaped switch block (WMSB), proving (4, 4)-WMSB with 24 switches is optimal. Furthermore, we also propose optimal (4, 7)-WMSB, which is a (4, 7)-HUSB with 42 switches.

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. This paper presents a novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems. The proposed design employs a low-cost computation scheme to enable 1536-point FFT, which significantly reduces hardware costs as well as power consumption. In conjunction with the aforementioned 1536-point FFT computation scheme, the proposed design included an efficient three-stage SDF pipeline architecture on which to implement a radix-3 FFT. The new radix-3 SDF pipeline FFT processor simplifies its data flow and is easy to control, and the complexity of the resulting hardware is lower than that of existing structures. This paper also formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme. The proposed design was implemented using 90 nm CMOS technology. Postlayout simulation results revealed a die area of approximately 1.44×1.44 mm2with power consumption of only 9.3 mW at 40 MHz.

This paper proposes theories of the design of multi-point interconnection networks, and then develops a switching network scheme which efficiently interconnects FPGAs in Symmetric Programmable Multi-FPGA Systems. A new four-side, hyper-universal switch box is introduced which, satisfying routing resource constraints, is routable for all possible surrounding multi-pin net topologies. This paper proves that when the number of the terminals on each side is greater than 23, the new switch box demonstrates better switch-efficiency than Fan's switch boxes. This paper also presents a formal analysis and extensive experiments on routability comparisons among some of the most well-known FPGA switch boxes such as disjoint switch boxes, Wilton's switch boxes, universal switch boxes, Fan's switch boxes and the new hyper-universal switch networks.

This work applies perfect-shuffle on software defined radio's bit-shuffling blocks, such as puncturer and interleaver, which data alignment issue is also investigated. A demonstration of such algorithm on IEEE 802.11a (WiFi) standard is implemented with Texas Instruments®intrinsic perfect-shuffle and inverse perfect-shuffle instructions combined with ANSI C on a TMS320 C64x digital signal processor. Simulation results indicate the performance enhancement using perfect-shuffle technique dramatically improved cycle efficiency comparing to a naive one bit per integer implementation.

This paper demonstrates a multi-band low noise amplifier (LNA) in 0.13µm CMOS process, which is configurable with switching capacitor in 900MHz, 1800MHz, 2.4GHz and 5.2GHz bands. A dual-loop feedback technique is used to enhance the performance in noise figure, power gain and power consumption. The noise figures are 2.6dB at 900MHz, 2dB at 1800MHz, 2.1dB at 2.4GHz and 3.5dB at 5.2GHz; and the power gains are 17dB at 900MHz, 21dB at 1800MHz, 26dB at 2.4GHz and 19dB at 5.2GHz in post-simulation. The S11in all of the bands is below −10dB by wideband matching. The LNA consumes 3.92mW from 1 V supply.