Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the simulations for discrete-time /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in today's low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of continuous-time /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators as needed in top-down design and high-level modulator optimization. The method is based on analytical integration using behavioral models and exhibits the best tradeoff between accuracy, speed, and extensibility in comparison with other possible techniques that are reviewed briefly in this work. This methodology has been implemented in a user-friendly tool. Nonidealities such as finite gain, finite GBW, output impedance, and also nonlinearities, such as clipping, harmonic distortion, and the important effect of jitter are modeled. Finally, the tool was used to carry out some design-relevant experiments, illustrating the straightforward way of obtaining and exploring design tradeoffs at the modulator architectural level.

An approach is presented for the high-level simulation and synthesis of discrete-time /spl Delta//spl Sigma/ modulators based on a simulation-based optimization strategy. The high-level synthesis approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications-mainly accuracy (dynamic range) and signal bandwidth-are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator to realistically analyze and optimize the modulator performance. The approach has been implemented in a tool called Daisy (Delta-Sigma Analysis and Synthesis). Experimental results are shown for both the analysis and synthesis capabilities, illustrating the effectiveness of the approach. The selected range of optimized /spl Delta//spl Sigma/ modulator topologies as a function of the modulator specifications for a wide range of values indicate the capabilities of and the performance range covered by the tool.

To reduce the long circuit-level simulation time of /spl Delta//spl Sigma/ modulators, a variety of techniques and tools exist that use high-level models for discrete-time (DT) /spl Delta//spl Sigma/ modulators. There is, however, no rigorous methodology implemented in a tool for the continuous-time (CT) counterpart. Therefore, we have developed a methodology for the high-level simulation of CT /spl Delta/E modulators and implemented this method in a user-friendly tool. Key features are the simulation speed, accuracy and extensibility. Nonidealities such as finite gain, finite GBW, output impedance and also the important effect of jitter are modelled. Finally, experiments were carried out using the tool, exploring important design trade-offs.

Circuit--level simulation of ΔΣ modulators is a time--consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete--time (DT) ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous--time (CT) counterpart. Yet, in todays low--power, high--accuracy and/or very high--speed demands for A--to--D converters, designers are often forced to resort to the use of CT ΔΣ topologies. In this paper, we present a method for the high--level simulation of continuous--time ΔΣ modulators that is based on behavioral models and which exhibits the best trade--off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user--friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade--offs.

An integrated tool called DAISY (Delta-Sigma Analysis and Synthesis) is presented for the high-level synthesis of /spl Delta//spl Sigma/ modulators. The approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications mainly accuracy and signal bandwidth-are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator that includes the major nonidealities of the building blocks to realistically analyze and optimize the modulator performance. Experimental results illustrate the effectiveness of the approach. Also, an overview of optimized topologies as a function of the modulator specifications for a wide range of values shows the capabilities and performance range covered by the tool.