Wireless Internet-access technologies have significant market potential, particularly the Worldwide Interoperability for Microwave Access (WiMAX) protocol which can offer data rates of tens of megabits per second. A significant demand for embedded high-performance WiMAX solutions is forcing designers to seek single-chip multicore systems that offer competitive advantages in terms of all performance metrics, such as speed, power, and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an application-specific integrated circuit, emerging dynamically reconfigurable (DR) processors are proving to be strong candidates for processing cores in future high-performance multicore-processor systems. This paper presents several new single-chip multicore architectures for the WiMAX application based on recently emerging coarse-grained DR processor cores. A simulation platform is proposed in order to explore and implement various multicore solutions combining different memory architectures and task-partitioning schemes. This paper describes the different architectures, the simulation environment, and several task-partitioning methods and demonstrates that up to 7.3 and 12 times speedup can be achieved by employing eight and ten DR processor cores for both the WiMAX transmitter and receiver sections, respectively. A comparison with other WiMAX multicore solutions is given in order to demonstrate that our best solution delivers a high throughput at relatively low area cost.

Wireless internet access technologies such as WiMAX have significant market potential. The high demand for embedded high performance WiMAX solutions is forcing designers to seek multi-core systems which offer competitive advantages in terms of all performance metrics. By providing the flexibility of a DSP with performance and power consumption approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be stronger candidates than conventional general-purpose processors or DSPs for future multi-core systems. This paper presents several multi-core solutions, based on newly emerging dynamically reconfigurable processor cores targeting WiMAX based applications. Coming with a SystemC trace-driven multi-core simulator, a simulation platform has been proposed in order to explore and implement various multi-core solutions combining different task partitioning strategies and inter-process communication methods.

Stream processing applications such as image signal processing demand high throughput. However, customers increasingly demand runtime flexibility in their designs, which cannot be provided by custom ASIC solutions. Currently, reconfigurable processors tend to offer insufficient throughput for widespread use in streaming applications. This paper demonstrates how structural-level pipelining techniques can be applied to rapidly dynamically reconfigurable computing architectures, in order to increase throughput. This is done by automatically inserting registers into the datapath of performance critical code sections that have already been optimised into a single configuration context. A new algorithm is presented to choose the insertion point of pipeline stage registers in order to meet a specified throughput whilst minimising register resource usage. The paper then demonstrates a new approach where properties of dynamic reconfiguration can be utilised to perform the tasks of pipeline stage initialisation and flushing. The technique is demonstrated on a real-life application: the demosaic filter in a standard image signal processing pipe used in modern digital cameras, and can be seen to boost the throughput from 16MPixels/s to 51MPixels/s on an example reconfigurable processor.

This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.

This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high performance, high flexibility and ANSI-C support. WiMAX physical layer program has been implemented on the target architecture with the RTOS support. A semaphore based synchronization scheme is used to improve the task independence. The research lays a foundation for further exploration of multithreading on multiple target architectures.

This paper presents a new direct implementation of a popular RTOS with an associated application - the WiMAX physical layer - on reconfigurable computing architectures. A novel coarse-grained reconfigurable instruction cell based architecture is chosen as the target architecture. Firstly an RTOS - Micro C/OS-II - was ported to the target architecture, and then the WiMAX physical layer program was partitioned into multiple OS tasks which communicate with each other through the synchronization approaches provided by this RTOS. The WiMAX physical layer program has been also implemented on the ARM7TDMI processor. The results show that the performance of the target architecture is much better than the ARM7TDMI, and not limited by the bottleneck of memory latency.

We present a new De-Blocking Filter module fully optimised for use on a recently introduced dynamically reconfigurable, instruction cell based architecture. The module consists of a novel combination of standard software transforms alongside architecture specific techniques and aims to reduce reconfiguration overheads and increase utilisation of resources. Our proposed filter outperforms the standard FFMpeg based filter code on the target architecture by 4.5 times.

This paper presents the preliminary results of a physical placement algorithm for heterogeneous Dynamically Reconfigurable Arrays (DRA), based on a multi-objective, multi-threaded GA. The algorithm deals with the spatial and temporal nature of the configurations used in DRAs, in an attempt to find a suitable layout for a wide range of applications, since general applicability is a key criteria for DRAs.