This paper presents a new concept for accurate modeling and timing simulation of electronic systems integrated in a typical VHDL design environment, taking into account the requirements of deep submicron technology.Contrary to conventional concepts, autonomous models for gates and interconnections are used.A piece-wise-linear signal representation allows to model waveform dependent effects.Furthermore, the gate models catch pattern dependencies, the models of interconnections take into account post layout information with rami ed structure, dierent layers and even contact holes.

Designer's productivity has become the key-factor of the development of electronic systems. An increasing application of design data reuse is widely recognized as a promising technique to master future design complexities. Since the intellectual property of a design is more and more kept in software-like hardware description languages (HDL), successful reuse depends on the availability of suitable HDL reverse engineering tools. This paper introduces new concepts for an integrated HDL reverse engineering tool-set and presents an implemented evaluation prototype for VHDL designs. Starting from an arbitrary collection of HDL source code files, several graphical and textual views on the design description are automatically generated. The tool-set provides novel hypertext techniques, expressive graphical code representations, a user-defined level of abstraction, and interactive configuration mechanisms in order to facilitate the analysis, adoption and upgrade of existing HDL designs.