The job-shop scheduling problem is concerned with allocating limited resources to operations over time. Although the job shop scheduling has an important role in various fields, it is one of the most difficult problems in combinational optimization. In this paper, we propose a new scheduling technique that combines Ant Colony Optimization (ACO) with GT method in order to realize effective scheduling. ACO approach has been applied recently to several combinational optimization problems, e.g., TSP and scheduling problem. However, no studies have ever seen the approach of applying hybrid ACO to job-shop problems. Experimental results using benchmark data show improvement comparison with a conventional scheduling technique.

Deep-sub-micron (DSM) technology of 0.18 microns and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, it is important to optimize timing constraint, power consumption and chip area at initial phase of layout design. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on genetic algorithms has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving chip area, interconnect delay and power consumption. Moreover, we introduced a novel approach based on collaboration of software and hardware in order to reduce the run time. Experimental result shows improvement comparison with commercial EDA tool.

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the dominant design phase. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on genetic algorithms (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving chip area, interconnect delay and power consumption. In order to reduce run time, the two kind of parallel processing suitable for hierarchical processing is introduced. Experimental results show improvement comparison with commercial EDA tool.

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel congestion-driven placement technique based on asynchronous parallel genetic algorithm. The proposed algorithm has a two-level hierarchical structure. For selection control, new objective functions are introduced for wire congestion and chip area. Moreover, the two kind of parallel processing suitable for hierarchical processing is introduced for reduction of run time. Experimental results show improvement comparison with conventional layout technique.

Genetic Algorithm (GA) is widely known as a general-purpose optimization method, which can provide sub-optimum solutions for various. optimization problems by means of modeling genetic evolutionary process of creatures. Several essential difficulties exist in GA, however, with regard to large amount of computation time, premature convergence in early stage of evolution and proper adjustment of many GA parameters. In order to overcome the difficulties of GA, this paper describes the architecture of a scalable and high-speed GA processor, which is characterized by hardware-oriented approach based on Distributed GA, optimized hierarchic pipelines for high-speed evolutions and flexible genetic operations corresponding to a given problem. Furthermore, this paper also describes VLSI implementation of a processor-element to verify feasibility of our proposed architecture for applications.

This paper outlines the concepts and the key technologies of design automation for developing high-performance microprocessor chips. The goals of the design automation system are twofold: (1) reducing the development period, (2) implementing high performance. Problems in design automation include concurrent verification of both logic and timing design, incremental physical design, and a cooperative timing-driven placement and a routing procedure which accept various designer's specifications. Solutions to these problems are presented.

This paper outlines the concepts and the key technologies for designing high-performance mainframe computers.The goals of the design automation system are:1) reducing the development period, 2) implementing high performance.We perceive that both of the goals must be achieved for the timely development of mairtframe computers that meet the market demand.The latest high-performance mainframe computer, the Hitachi M-880, was successfully designed by utilizing this system, and total capability of the system has been proven.

Placement algorithms optimizing signal delay as well as wirability for high-speed ECL masterslice LSI's are proposed. Equivalent constraints of wire length for clock skew, data path delay, and wired-OR are classified according to upper and lower limits. To maintain such limits, a top-down method utilizing an augmented two-dimensional clustering placement with “scope” and “zone”, which are new concepts representing limits, and an iterative weighted improvement method are presented. Such algorithms are applied to hundreds of 2 K and 5 K gate ECL masterslice LST's for a newly developed high-end mainframe computer, the Hitachi M-680H. Through such algorithms, the physical design is greatly improved by guaranteeing high wirability and improving electrical characteristics.

Routing algorithms for multi- (more than 3) sided pin arrangements are presented. These algorithms are essential for layouts mixing standard cells with custom macros such as ROM, RAM, PLA and ALU. An extended layout model in which these algorithms are applied is also presented. An experimental result regarding the effect on block area with respect to cell height, obtained by comparing an extended model with a traditional model, is described.