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W. W. Wong

dblp:70/5326 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.011994
JFET circuit simulation using SPICE implemented with an improved model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Integrated circuit design › analog and mixed-signal circuits
device modeling
0.011994
JFET circuit simulation using SPICE implemented with an improved model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › circuit simulation › analog circuit simulation
SPICE simulation
0.011994
JFET circuit simulation using SPICE implemented with an improved model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

physics-based modeling · 0.0parameter extraction · 0.0
YearPublicationVenuePosition
1994 JFET circuit simulation using SPICE implemented with an improved model
abstract
Junction field-effect transistor (JFET) circuit simulation using an existing physics-based JFET model is presented. This improved model has more predictive capability than the conventional JFET model employed in SPICE. Furthermore, it treats the linear and saturation regions in a unified manner and includes the subthreshold behavior, an effect not accounted for in the conventional model. The improved model is implemented into PSPICE run on a Sun workstation, and steady-state and transient responses are simulated for a JFET switching circuit and a JFET voltage follower circuit. Results obtained from the improved model compare favorably with that obtained from a two-dimensional device simulator PISCES and from measurements. For JFETs operating outside the subthreshold region, the conventional model with optimized parameters (extracted from measurements) also shows good accuracy. However, large discrepancies arise from the conventional model if JFETs are biased in the subthreshold region or if default model parameters are used.>
W. W. Wong, Juin J. Liou
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1