We describe methods to use PLL-based transition test in support of chip bring-up. We used it to diagnose slow paths for performance improvement. During bring-up, often the issues of setup, design, scan patterns, and silicon slow paths are mixed together, making diagnosis more difficult. We discuss techniques used to understand and resolve these issues, and show examples of the benefit of transition test over functional and system test.

Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths. This paper describes our experiments indicating that this is not always the case. For the UltraSPARC T2 microprocessor series we found that transition delay test often ran slower, was more effective in finding the root cause of the slow path, and correlated well with functional diags also used for speed binning. Transition test does a better job finding delay issues related to the impact of simultaneous switching and coupling noise on chip speed. We used transition test to measure the impact on chip timing of voltage, temperature, and we also used it to confirm the results of improving slow paths.

Sun's T2 processor transition test methodology, verification and silicon debug are described. We illustrate our test mechanism, test sequence, test development, and the verification of this mechanism in silicon. Methods to identify slow flops, diagnose gate dominated paths, excite long delay for wire dominated paths, and find essential patterns for speed characterization are presented. In addition, a method is developed for recovering devices with a fewer good processor cores. All these applications together make transition test a much more powerful tool.

As the complexity of microprocessors increases, the design and bring-up times have significantly increased, negatively impacting the time-to-market (TTM) requirements. In this paper, a backtracing methodology for identifying the root cause of functional failures on the UltraSPARCtrade family of processors is presented. Data provided by a scan dump analysis methodology is linked not only to the design database but also to the failing test in order to isolate one or several candidates for further analysis

This paper presents an approach for analysis of system state differences observable through the scan chain for the debug of functional failures. A novel methodology for Latch Divergence Analysis (LDA) is proposed for creating stable failure signatures and reducing system noise. The methodology and processing flow have been integrated into the normal debug flow for the UltraSPARCTM family processors and have been successfully applied in numerous debugs in the bring-up of new products.

This paper investigates the degradation in detectability of bridging faults caused by situations of active feedback and logically unresolvable intermediate values under different fault modeling assumptions. A bridging fault simulator is presented that is based on a combination of switch-level modeling and levelized logic simulation. Levelized simulation is efficient for fault propagation and feedback analysis, whereas the switch-level model is used for determining whether an intermediate value is logically resolvable. A method to extract the logic function of channel graphs is presented in order to perform levelized processing of switch-level networks. The experimental results show that active feedback may reduce fault coverage by as much as 9% for stuck-at test sets and realistic bridging fault sets.

To simulate the effects of feedback bridging faults accurately, it is necessary to take into account both the conflict between signals of opposite logic values and the oscillation or asynchronous behavior induced by global feedback loops. This papers presents a method for detecting and processing global feedback dynamically in logic simulation. The problem of asynchronous behavior in feedback paths with an even number of inversions is solved by breaking the feedback and evaluating the possible stable states separately. Simulation experiments show that the uncertainty in fault diagnosis can be significantly reduced by incorporating the proposed technique for feedback analysis.

Logic-level modeling of asynchronous circuits in the presence of races frequently gives rise to oscillation.A new method for solving oscillation occurring in feedback loops (FLs) is presented.First, a set of graph traversal algorithms is used to locate the FLs and order them with respect to a dominance relation.Next, a sequence of resimulations with the feedback vertices forced into stable states is performed.The proposed method can handle noncritical races occurring in asynchronous circuits and has applications in feedback bridging fault simulation.

An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.

Short faults in CMOS networks frequently give rise to intermediate node voltages. An efficient local algorithm is presented for event-driven switch-level simulation of CMOS networks in which intermediate signal values are common. The proposed model allows multiple dominant signals associated with the state of a node. The strength of several logical low and high signal contributions can thereby be taken into account when the logic state of a node is computed, which means that intermediate voltages can be handled more accurately. To demonstrate the usefulness of the multiple-dominance model in fault simulations, a new fault simulation algorithm is presented. Various common transistor-level fault types were simulated, and the results show that the number of discrepancies from electrical-level simulations is significantly reduced at a low computational cost.

Transistor gate stuck-at and node stuck-at faults in self-testing checkers of various implementations are examined. Two types of CMOS implementations with different transistor driving strength ratios are considered. The coverage obtained for the classic gate-level stuck-at fault model for different test set sizes is compared with the corresponding coverage of transistor-level faults. It is shown that the coverage estimation using the gate-level stuck-at model is overly optimistic.

Two new switch-level algorithms with efficient management of unknown values are evaluated with respect to their fault modeling capability. The degradation of confidence in fault detection measures owing to unknown (X) output values is discussed and a strategy to quantify this uncertainty is proposed. It is demonstrated that this uncertainty can be decreased significantly when the node model is extended to include two resistances.

Abstract- An algorithm is presented for event-driven switch-level simulation of CMOS networks in which intermediate signal values are common. The proposed method is based on a local signal propagation scheme and an extended node model including both a logical low and a high contribution to the state of a node. The quantization effects of typical CMOS networks can thereby be modeled and, hence, the spread of undetermined logic values is in many cases prohibited. I.

The presence of realistic faults in CMOS networks, such as shorts and opens, frequently gives rise to intermediate voltage values. At the switch level, these values result in undetermined logic states which are likely to propagate to the outputs, causing an overly optimistic coverage estimation of test efficiency. A new method is presented that is efficient and well-suited for modeling switch-level networks when undetermined states are common. The concept of state dominance, introduced in this paper, is an improvement upon the well-known principle of dominance. The state dominance defines a dynamic direction of signal flow between neighboring nodes of undetermined logic state. A signal transformation scheme is proposed which solves bidirectional conflicts that may occur between adjacent nodes of undermined logic state without any network recomputation. The new concept is easily applicable to switch-level algorithms in which there is a distributed approach.

Several realistic transistor fault models were applied to circuit-level simulation models of code checkers in order to investigate the run-time fault testing capability. Various implementations of checkers designed for the detection of stuck-at faults were examined. A coverage varying from 99% to 100% was obtained for transistor terminal short faults and from 40% to 85% for open faults. A minimum set of four fault models for simulation-based evaluation of the self-testing property is proposed.