Nanometric scaling steadily increases failure rates, which are particularly acute for ultimate complementary metal–oxide–semiconductor (CMOS) and post-CMOS devices. We previously established an ECC-based method of memory repair that dramatically reduced the cost for high fault rates, and in this article, we establish a repair architecture that further reduces the power cost. Since CAMs are power hungry (as the address of each memory operation is compared with all the tag fields), we use a cache with the following innovations: 1) innovative repair architecture: although a direct-mapped cache and a set-associative cache that employs offset address bits are efficient for performance of CPUs, we show that they are inefficient for memory repair, since the characteristics of the memory words that need to be replaced in memory repair are different from the case of CPUs, and hence, rather than using any of these cache architectures, we establish an innovative memory repair method that uses another cache and an overflow block; 2) this architecture is thousand times more efficient than other approaches to memory repair based on a CAM or cache; 3) we present a yield computation that determines the size of each block of this repair architecture that is needed to achieve any target yield, and we establish this using a novel probabilistic approach, mathematical approaches and algorithms; and 4) at high fault rates, the yield computation is intractable; we make it tractable via an innovative recursive mathematical approach that significantly reduces the number of operations.

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. This paper describes the GRAAL architecture, which improves significantly the fault detection efficiency, cost, and timing constraints of the double-sampling approach, providing this way an efficient scheme for solving the issues induced by aggressive technology scaling in the era of ultimate-CMOS and post-CMOS technologies.

Memory system reliability is a serious concern in many systems today and is becoming more worrisome as technology scales, system size grows and the demand of aggressive voltage reduction becomes more stringent. Thus, disposing of memory repair architectures with strong fault tolerance capability at low cost is desirable. In this context, Error Correcting Codes (ECC)-based repair techniques were proposed and offer aggressive reduction of the repair cost for high defect densities. However, an important issue in advanced process nodes is the fact that, single particles induce Single-Event Upsets (SEUs) in neighbor memory cells, thus leading to Multi-Cell Upsets (MCUs) and Multi-Bit Upsets (MBUs), when they occur in the same memory word. In the case of memories, there exist efficient approaches mitigating this kind of MBUs, in particular the use of interleaving. But when a memory is repaired, the impact of MBUs on the circuitry repairing the faulty memory words should also be mitigated. This can be done by using a repair Content Addressable Memory (CAM) having interleaving at its data-words, or else an Offset CAM. In this paper we present and evaluate a novel repair approach that uses the Offset CAM in ECC-based Memory Repair and hence permits the mitigation of the MBUs affecting it.

In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield, as well as during lifetime to increase lifespan. In technologies affected by high defect densities, conventional repair induces very high cost. To reduce it, in previous work we proposed the ECC-based repair scheme, consisting in using the ECC for fixing words comprising a single faulty cell, and self-repair to fix all other faulty words. This approach is of high interest for ultimate CMOS and post-CMOS technologies, where the defect densities are expected to increase significantly, and/or in very-low power designs as very-low voltage sharply increases defect densities. However, we showed recently that, for high defect densities the diagnosis circuitry required for ECC-based repair may induce large cost. In previous work we addressed this issue by means of a new family of memory test algorithms that exhibit the so-called single-read double-fault detection (SRDF) property. The SRDF algorithms resolve the diagnosis issue at no area cost. However, as they are complex and increase test length, in this paper we explore a new diagnosis approach using iterative test execution, which, together with the SRDF test algorithms, provide a set of options enabling efficient tradeoffs in terms of hardware and power costs, and test length.

The double sampling paradigm is an efficient method to protect the circuits against soft-errors. But the data that are going out of the area protected by double sampling are still vulnerable. In this paper we proposed an architectural solution that uses three latches to remove those constraints and protect the area outside the double sampling domain without adding a buffer stage.

As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250×, while offering RTL-like accuracy. These promising results make our simulation method ideal for evaluating future NoCs comprising thousands of nodes.

3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. In addition, the number of vertical paths can be expected to be further reduced due to defects and runtime failures. To reliably route packets under such conditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected 3D-NoCs named “Rout3D”. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the East and North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. We combine our algorithm with a novel offline reconfiguration method requiring only 4 bits per router to maintain connectivity upon the occurrence of faults while minimizing the implementation cost. Simulation results reveal that our algorithm is capable of sustaining a very good level of performance compared to related works, in spite of using less virtual channels.

NoCs (Networks-on-Chips) are being viewed as the paradigm of choice for on-chip communication in modern SoCs (Systems-on-chips). Unfortunately, continuous technology downscaling is rendering NoC components increasingly susceptible to failure, to a point where it is no longer an option to design such systems without accounting for reliability issues. In this work, we concern ourselves with faults affecting one of the most important logical units in NoC routers, namely the Route Computation Unit. To prevent deadlocks and packet loss, which may result from misrouting, we propose a solution to detect and correct route computation errors. With compatibility with non-minimal fault-tolerant adaptive routing algorithms in mind, two detection methods are proposed. Lazy detection only detects the faults that may result in an error immediately following route computation, and leaves it to the next hops to detect and correct other errors. Strict detection detects all fatal errors before the affected packets leave the faulty router, making it possible to correct all errors using a single rerouting mechanism. Finally, we propose a novel method to safely correct routing errors and deliver all packets to their destination without resorting to retransmission.

Aggressive technology scaling has dramatic impact on process, voltage and temperature (PVT) variations; circuit aging and wearout; clock skews; sensitivity to EMI (e.g. crosstalk and ground bounce), sensitivity to radiation-induced SEUs SETs; as well as power dissipation and thermal constraints. The resulting high defect rates and design complexity, adversely affect fabrication yield and reliability.

In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after fabrication to achieve acceptable fabrication yield. In technologies affected by high defect densities, conventional repair induces very high costs. To reduce it, we can use ECC-based repair, consisting in using the ECC for fixing words comprising a single faulty cell and self-repair to fix all other faulty words. However, as we show in this paper, for high defect densities the diagnosis circuitry required for ECC-based repair may induce very large hardware cost. To fix this issue, we introduce a new family of memory test algorithms that exhibit a property we termed as “single-read double-fault detection”. This approach gains interest in ultimate CMOS and post-CMOS technologies, where the defect densities are expected to increase significantly, and/or in very-low power design, as very-low voltage sharply increases defect densities.

NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to increase the reliability and performance of NoCs. We combine these techniques to build a fault-tolerant, deadlock-free and congestion-aware routing algorithm called MUGEN. The algorithm comprises an optimized method to exchange messages between different virtual channel classes, a selection function that uses distant router link information to avoid dead-ends and a new congestion metric used to guide routing decisions towards less congested areas. We simulate an 8×8 Mesh NoC with fault injection to evaluate each method used by MUGEN individually before comparing the full algorithm with existing works from literature. We present promising results about the proposed techniques both in terms of fault-tolerance and performance.

We illustrate that memory repair for high fault rates can be exploited for improving yield, extending lifetime, reducing power, and improving reliability, and consequently can be used to push aggressively the limits of technology scaling. We also present recent advances in low-area and low-power memory repair for high fault rates. As one of our main goals is to use this repair for reducing as much as possible the power dissipation of the memory system, the power dissipation of the repair circuitry should be kept as low as possible. To comply with this constraint, we also propose a repair approach, which further reduces the power dissipation of the repair circuit.

We illustrate that memory repair for high defect densities allows improving yield, extending circuit life, reducing power, and improving reliability, and can be used to push aggressively the limits of technology scaling. Then we present several developments enabling low-cost memory repair for high defect densities, which alllow realising this promise.

The integration of more and more computing cores into processors drives the adoption of larger and larger Network-on-Chips (NoCs). Concurrently, the decreasing reliability of 1 the latest technologies promotes the utilization of fault-tolerant techniques. Unfortunately, the understanding of fault-tolerant NoCs is increasingly difficult as interconnect scale up, because they require the combination of more and more complex and heterogeneous techniques. In this paper, an high-level model named VOCIS is presented, in order to ease the comprehension and analysis of large unreliable NoCs. This model features a 3D Graphical User Interface (GUI), that offers an effective and in-depth visualization of interconnects. A few analytical measurements provided directly by VOCIS are also presented, in order to assess quantitatively the impact of defects and corresponding fault-tolerant techniques.

New CMOS processes offer cheaper but less reliable transistors. This trend foreshadows the apparition of processors consisting of hundreds and thousands of cores prone to defects. In this context, the performance of the core interconnect under faults will be critical. In this work, we propose the combination of a novel adaptive routing algorithm and several related router mechanisms, which firstly ensure message transfers under transient and permanent faults and second adapt to congestion in order to improve the interconnect performances. In effect, the widespread 2D mesh topology offers a high redundancy of routes. Hence, a fault-tolerant congestion-aware routing algorithm is able to improve substantially the interconnect efficiency under degraded conditions. Besides, the Virtual Channel allocation is optimized for performance, and a message truncation mechanism is added to cope with dynamic permanent and transient faults.

Forthcoming technology nodes are posing major challenges on the manufacturing of reliable (real-time) systems: process variations, accelerated degradation aging, as well as external and internal noise are key examples. This paper focuses on real-time systems reliability and analyzes the state-of-the-art and the emerging reliability bottlenecks from three different perspectives: technology, circuit/IP and full system.

The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. In this paper, an high-level method is proposed to map and manage a parallel application on an unreliable many-cores processor System on Chip subject to intra-die variability.

Nanometric scaling steadily increases failure rates, which are expected to be exacerbated as we are approaching the ultimate limits of CMOS and to worsen yet as we will engage in post-CMOS technologies. Moving towards ultimate CMOS and post CMOS also requires increasingly aggressive power reduction. An efficient way to reduce power consists in reducing voltage. Aggressive voltage reduction will result in increasing the numbers of weak memory cells that will operate falsely. Thus, it is desirable to dispose memory repair architectures able to cope with high defect densities. At the same time, reliability is another major concern with aggressive technology scaling. In this context, recent techniques combining memory repair architectures with ECC were able to aggressively reduce repair cost for high defect densities. However, even under the drastic cost reduction obtained with these approaches, power penalty can still be significant as we consider increasing levels of defect density. This paper proposes new repair architectures that are advantageously combined with the previously proposed solutions and allow drastic reduction of dissipated power.

The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. In this paper, an high-level method is proposed to map and manage a parallel application on an unreliable many-cores processor System on Chip. The approach takes into account versatile constraints relative to these processors (e.g. variability, core-level DVFS) and a generic algorithm is proposed. The distributed mapping process is based on the dynamic search of the best-suited processing node, upon task creation or node defect. An adaptive stop criteria is defined in order to balance the mapping impact and application efficiency gains. The validity of the proposition is assessed with high-level simulations, under different variability and application conditions.

A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under various case studies, with different permanent, transient and intermittent link faults, and under different failure rates demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies.

Embedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS processes, resulting in high defect densities. These problems will further worsen due to stringent low-power constraints requiring drastic reduction of voltage levels. To cope with the resulting high defect densities in cost effective manner, ECC-based repair combining ECC with spare words becomes mandatory. On the other hand, coping with accelerating aging may require testing the memories during application execution, making mandatory transparent BIST Nevertheless, traditional implementations of transparent BIST do not comply with the constraints of ECC-based repair. To cope with this issue the paper proposes a transparent BIST architecture compliant with ECC-based repair.

Today, there are several trends that are making the reliability analysis of complex integrated circuits an important challenge in industry. As transistor geometries shrink, the number of physical failure mechanisms is increasing while at the same time the number of transistors per chip is still growing. The rollout of new services is pushing compute demands both in handheld devices and in the data center which is driving up complexity and the level of integration. People are becoming critically dependent on mobile services and expect high availability. Looking forward to the deployment of the Internet of Things (IoT) where processors and routers will be embedded in billions of end-points, we are only going to see an increased demand for reliable computing. In this session, we bring together three different industrial perspectives on reliability. The first looks at the end-points, the second looks at the servers and the last looks at the economic drivers for reliability and the demand for new EDA tools for reliability analysis. In the first talk, Rob Aitken from ARM will discuss the reliability challenges in mobile applications. As mobile systems continue to increase in size and complexity, and user requirements are also becoming more stringent, it is important for designers of mobile systems to be aware of reliability issues, and to adapt their methodologies accordingly. This talk discusses the issues involved, from latent defects, through soft errors, aging and wearout, and shows how to consider these as part of the design process, how to quantify their effects, and how to mitigate them through design changes. In the second presentation, Burcin Aktan from Intel is going to discuss the evolution of the reliability features that are found in server applications. With so many processing units packed in data centers the reliability requirements on an individual device is growing, especially with integrated memory controllers and very high bandwidth data pathways. What was an “add-on” to a device function, 10–15 years ago, now needs to be considered carefully with stringent budgets distributed to each functional block that contribute to overall error rates. This talk will focus on the evolution of reliability features in a number of server products leading into the current state and look at how today's designers are dealing with the challenges of gathering requirements, translating these to design implementation and delivering quality features to customers. Finally we will close with remarks on future directions and possible research areas. In the final presentation, Olivier Lauzeral from iROC Technologies will discuss the importance of methodologies for the reliability analysis of complex SoCs. There is an inherent cost to adding reliability features in a complex IC and designers need to be able to make informed decisions about how much hardware to allocate for mitigation (redundancy, error correction, repair). A prerequisite to make such choices is clearly defined targets and this requires an economic framework where the cost of failures is understood. Once the reliability targets for a system and individual devices are established, there is a need for EDA tools which allow designers to compute the failure rate and failure modes within the device. This analysis must include all failure mechanisms (radiation effects, lifetime effects, manufacturing detects) and take into account the relevant de-ratings between faults and observed errors. This new EDA infra-structure is key for designers to make effective trade-offs in order to arrive at a cost effective design.

In modern SoCs embedded memories should be repaired to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. In technologies affected by high defect densities, conventional repair induce very high costs. To reduce them, we can use ECC to fix words comprising a single faulty cell and repair to fix all other faulty words. However it was shown that, for high defect densities, the diagnosis required for ECC-based repair may induce very large cost. In previous work this issue was fixed by means of new memory test algorithms that exhibit the so-called “single-read double-fault detection” property. As these algorithms are complex and increase test length, we explore a new iterative diagnosis approach, which provides tradeoffs in terms of hardware cost and test length.

This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14 nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.

In this paper, a new standard language called RIIF (Reliability Information Interchange Format) is defined which enables designers to specify the failure characteristics and reliability requirements for simple and complex components. This language enables EDA tools to analyze reliability models and to compute the failure rates for complex systems. A formal language makes it possible for suppliers and consumers to exchange reliability information in a consistent fashion and to use this information to build accurate reliability models. The RIIF language is a general purpose reliability modeling language and is not tied to a specific application domain or implementation technology.

Three-dimensional (3D) integration by die-/wafer-level stacking becomes a reality, as Through-Silicon-Via technologies emerge. However, poor reliability and yield of TSV interconnects remain major challenges of this promising technology. In this paper, we propose an efficient Built-In Self-Repair (TSV-BISR) strategy for TSV faults due to manufacturing and aging defects. After interconnect tests, we replace faulty TSVs with fault-free spares using shift operations. Among the benefits of this solution is that the self-repair signals are determined on-chip without any external intervention. Moreover, we show that with TSV-BISR better reparability is achieved with fewer spares than in existing TSV repair techniques. We also show that for 3D chips with interconnect reparability targets above 98% we reduce the area needed for spares and repair logic by up to 40%.

In modern SoCs embedded memories should be repaired after fabrication to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. To avoid paying the area and power penalties of both approaches, we can use ECC to fix both fabrication and field failures. However, we show that efficient implementation of this approach may require special diagnosis hardware or new memory test algorithm that exhibit the so-called “single-read double-fault detection” property defined in this paper. We also propose test algorithms satisfying this property.

Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, the Deep submicron technology foreshadows highly defective chips era. In this context, not only fault-tolerant designs become compulsory, but their performance under failures gains importance. In this paper, we present a deadlock-free fault-tolerant adaptive routing algorithm featuring Explicit Path Routing in order to limit the latency degradation under failures. This is particularly interesting for streaming applications, which transfer huge amount of data between the same source-destination pairs. The proposed routing algorithm is able to route messages in the presence of any set of multiple nodes and links failures, as long as a path exists, and does not use any routing table. It is scalable and can be applied to multicore chips with a 2D mesh core interconnect of any size. The algorithm is deadlock-free and avoids infinite looping in fault-free and faulty 2D meshes. We simulated the proposed algorithm using the worst case scenario, with different failure rates. Experimentation results confirmed that the algorithm tolerates multiple failures even in the most extreme failure patterns. Additionally, we monitored the interconnect traffic and average latency for faulty cases. For 20×20 meshes, the proposed algorithm reduces the average latency by up to 50%.

Drastic device shrinking, power supply reduction, increasing complexity and increasing operating speeds that accompanying technology scaling have reduced the reliability of nowadays ICs. The reliability of embedded memories is affected by particle strikes (soft errors), very low voltage operating modes, PVT variability, EMI and accelerated circuit aging. Error correcting codes (ECC) is an efficient mean for protecting memories against failures. A major issue with ECC is the speed penalty induced by the encoding and decoding circuits. In this paper we present an effective approach for eliminating this penalty and we demonstrate its efficiency in the case of an advanced reconfigurable OFDM modulator).

In 3D integrated systems, Thru-Silicon-Vias (TSVs) enable higher performance and energy efficiency, by reducing the data travel distances. However, the TSV manufacturing and wear-out defect rates lead to poor interconnect reliability and yield. The high fault rates and TSV footprint make spare-based repair solutions inefficient. I-BIRAS combines self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization. The design parameters are the number of data bits n, the number of spare TSVs r, and the minimum acceptable number mLIMIT of fault-free TSVs. If the number of fault-free TSVs is less than mLIMIT then the link assumed failed.

Soft errors have been emerged as an important reliability concern of modern ICs. In this work we have implemented an efficient error detection scheme in a low power DSP/MCU processor. Our scheme achieves high error detection efficiency at low hardware cost by means of an original combination of double-sampling and latch based-design into the so-called GRAAL architecture. The implementation of our design in 65nm and 45nm process nodes has confirmed the advantages of the GRAAL architecture: low area and power penalties and negligible performance degradation. Its high error detection efficiency was demonstrated by performing extensive simulations of single-event transients (SETs).

The reliability of modern Integrated Circuits is affected by nanometric scaling. In many modern designs embedded memories occupy the largest part of the die and are designed as tight as allowed by the process. So they are more prone to failures than other circuits. Error correcting codes (ECC) are a convenient mean for protecting memories against failures. A major drawback of ECC is the speed penalty induced by the encoding and decoding circuits. In [5], we propose an architecture eliminating ECC delays in both read and write paths. However, this previous work does not describe a generic set of rules enabling inserting the delay-free ECC in any design. In this paper, we present the key points of an algorithm and a related tool automating its implementation.

The advent of the Deep Submicron technology opens the way to many-cores processor chips. However, the variability and reliability of these processes poses new challenges. In particular, the mapping of applications will require specific strategies to leverage the plenty and diversity of the computation cores. In this work, a high-level study of the variability impact on Thousands-core processors is proposed for future technologies, based on the state-of-art VARIUS model. While many crucial details are yet unknown for these technologies, we suggest several scenarios, based on the existing literature. The obtained results are particularily suitable for Embedded Streaming applications, which both require high performance and low energy consumption. In this regard, generic task mapping strategies are proposed to improve the energy efficiency of the applications, and compared for a synthetic application. The Nearest node strategy is used as a baseline, and minimizes the communication overhead. Then, a novel energy criterion is introduced to balance the computation and communication energy consumption. While increasing the communication energy, this strategy reduces the overall consumption by up to 20%. Finally, a mapping strategy based on variability regions improves slightly the energy efficiency of the application in the presence of systematic variations.

In modern SoCs embedded memories concentrate the majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test, leading to field failures due to the use of faulty components in final products. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage for a increasingly complex faults. Fixing the test algorithm during the design phase may not be compatible with this goal, as unexpected failures not covered by this algorithm may be occur during production. Also, having the possibility to select the memory test algorithm after fabrication is very important during the initial phase of a new process node (both process debug and production ramp-up). Programmable BIST approaches, allowing selecting after fabrication a large variety of memory tests, are therefore desirable, but may lead on unacceptable area cost. BIST approaches enabling test algorithm programmability and data background programmability at low area cost have been presented in the past. However, no proposals exist for programming the address sequence used by the test algorithm. In this paper we expend programmable BIST to include address programmability. This new feature is implemented at low cost by using the memory under test itself to store the desired address sequence and some compact circuitry that enables using this sequence for testing the memory.

In this paper, a Self-Recovering strategy, which is able to "re-map" dynamically application tasks on a multi-core system, is presented. Based on run-time failure aware techniques, this Self-Recovering strategy guarantees seamlessly termination and delivering the expected results despite multiple node and link failures in a 2D mesh topology. It has been demonstrated, based on a statistical analysis, that the proposed technique is able to re-map the tasks of faulty nodes in a bounded number of steps. The theoretical results have been validated by simulations. The proposed technique is allowing to bypass multiple nodes, routers and links failures with a predictable number of hops. It has been demonstrated that the Motion JPEG-2000 application can be parallelized and formally represented as a Directed Acyclic Graph (DAG). It is worth noting that the proposed technique has been validated by the simulation of a 1000 cores system, in the presence of nodes and links failures up to 10%. Therefore, the proposed technique has been shown to be efficient for seamless execution of parallel streaming applications and to provide the Execution Time Reduction Ratio close to ideal.

Nanocomputing technologies hold the promise for higher performance, lower power consumption as well as increased functionality. However, the dependability of these unprecedentedly small scale devices remains uncertain. The main sources of concern are: • Nanometer devices are expected to be highly sensitive to process variations. The guard-bands used today for avoiding the impact of such variations will not represent a feasible solution in the future. Thus, timing errors may occur more frequently. • New failure modes, specific to new materials, are expected to raise serious challenges to the design and test engineers. • Environment induced errors, like single event upsets (SEU), are likely to occur more frequently than in the case of conventional semiconductor devices. • New hardware redundancy techniques are needed to enable development of energy efficient systems. • The increased complexity of the systems based on nanotechnology will require improved computer aided design (CAD) tools, as well as better validation techniques. • Security of nanocomputing systems may be threatened by malicious attacks targeting new vulnerable areas in the hardware.

The high defect rates of the TSV manufacturing processes lead to poor yield. Interconnect repair and serialization techniques were proposed to improve yield. In these papers the control of the repair and serialization circuitry are determined off-chip and are stored in one-time-programmable memories. In this work we present an Interconnect Built-in Self-Repair and Adaptive-Serialization approach (I-BIRAS), where interconnect repair and data serialization/deserialization is performed without external intervention (reducing cost of external equipment) and can be executed at any time (after fabrication and all along system life), thus coping with both fabrication and system-life defects.

Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, as the Deep submicron technology fore- shadows highly defective chips era, fault-tolerant designs become compulsory. In particular, the fault tolerance of a core interconnect is critical, and inevitably increases its complexity. In this paper, we present a novel adaptive routing algorithm that is able to route messages in the presence of any set of multiple nodes and links failures, as long as a path exists. Compared to the existing solutions, the proposed algorithm provides fault tolerance without using any routing table. It is scalable and can be applied to multicore chips with a 2D mesh core interconnect of any size. The algorithm is deadlock-free and avoids infinite looping in fault-free and faulty 2D meshes, based on Virtual Networks and Virtual Channels. We simulated the proposed algorithm using the worst case scenario, regarding the traffic patterns and the failure rate up to 40%. Experimentation results confirmed that the algorithm tolerates multiple failures even in the most extreme failure patterns. Additionally, we monitored the trade off between the fault tolerance and the average latency for faulty cases, as measurement of the performance degradation. The algorithm detects the interconnects partitioning and enables "preferred paths" for streaming applications.

As already witnessed today, and as foreseen, concerns attached to hardware will play an increasing role in the design and assessment of dependable and secure computing systems.

As technology scales, designing a massively parallel multi-cores system atop less reliable hardware architecture poses great challenges for researchers and designers. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. We present a variation-aware multi-level scheduling and power management methodology for application-specific multiprocessor system-on-chip (MPSoC) to mitigate the impact of process variations and to optimize the power consumption. The methodology combines both static and dynamic scheduling and tackles the scheduling problem at several abstraction levels according the granularity of the application tasks, processing nodes and the on-chip communication network. The first levels of scheduling allow the local optimization, design space exploration and take into account the variations parameters. The last level, is based run-time scheduling, allows dynamic power management and global on-line optimization.

As we move deeper in the nanotechnology era, computer architecture is solicited to manipulate tremendous numbers of devices per chip with high defect densities. These trends provide new computing opportunities but efficiently exploiting them will require a shift towards novel, highly parallel architectures. Fault tolerant mechanisms will have to be integrated to the design to deal with the low yield of future nanofabrication processes. In this paper we consider multi processor grid (MPG) architectures that assure scalability beyond hundreds of cores per chip. We study self-diagnosis and self-configuration methods at the architectural level and propose an enhanced self-configuration methodology that enables usage of a maximum percentage of available fault-free cores in MPGs with high defect densities. We show that our approach achieves usability of all fault-free cores for the case of fault-free routers whereas previous work was efficient for defect densities of up to 20-25% of defective cores. We also address the case of faulty routers, achieving usability of almost all fault-free nodes (fault-free cores having a fault-free router) for very high defect densities both in the cores and in the routers.

There is still a strong demand for solutions to improve dependability and security. Issues at stake include threats ranging from managing complexity and manufacturing defects to accelerated aging and susceptibility to environment disturbances. These solutions extend beyond hardware, microelectronics or physics; major computing- related issues spanning various aspects are also essential: architecture, networks, communication, synchronization, task parallelization, etc. The workshop is aimed at further characterizing these impairments and threats, as well as distinguishing possible alternative design approaches and operation control paradigms that have to be enforced and/or favored in order to keep achieving dependable and secure computing. Finally, it is worth pointing out that besides design techniques aimed at providing dependable and secure computing, assessment techniques (risk evaluation, validation, testing, etc.) should also play a fundamental role! For all these reasons, we believe that DSN is an ideal forum to address all these issues and foster fruitful exchanges on a long term basis.

Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. The JEDEC JESD89A standard was developed to tackle the accuracy and common metric issues of soft error qualification based on radiation testing. System designers can request component providers to assess the soft error rate (SER) of their components on the basis of this standard. This open meeting will bring experts from academia and industry (IC vendors, IDMs, silicon vendors, system vendors, fabless companies, ...) to discuss the needs and initiate IEEE task force for developing benchmarks and standards in the software-based SER qualification domain.

CMOS nanometric technologies are increasingly sensitive to soft errors, including SEUs affecting storage cells and SETs initiated in the combinational logic, and eventually captured by some latches or flip- flops. SEUs affecting latches or flip-flops are by far the largest soft error rate (SER) contributor in logic. Thus, developing cost-efficient hardened storage cells to cope with SEUs in latches and flip-flops (but also in some memories difficult to protect by ECC ) is of increasing importance. This paper proposes a new principle for designing low-cost highly robust storage cells and several transistor level implementations.

The continuous advances and progress made in hardware technology makes it possible to foresee a realm of unprecedented performance levels and new application-driven architectural designs, as evidenced by the recent announcement of a 80-core chip [1]. Nevertheless, the evolution of nanotechnologies raises serious challenges with respect to both dependability and security viewpoints. Issues at stake go far beyond developing protections with respect to accidental disturbances in operation, they also relate to the unreliability and variability that will characterize emerging nanoscale devices. Accounting for malicious threats targeting hardware circuits will constitute another increasing concern.

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, power dissipation, fabrication yield, and reliability worsen steadily making further nanometric scaling increasingly difficult. These problems would stop further scaling of silicon-based CMOS technologies at channel lengths between 10 and 20 nm. But even before reaching this level of integration, these problems could become show-stoppers unless new techniques are introduced to maintain acceptable levels of power dissipation, yield and reliability. The paper describes the principles of GRAAL (global reliability architecture approach for logic), a new fault tolerant architecture for logic designs. This architecture is aimed to provide a global solution for mitigating the flaws of deep nanometric technologies related to power dissipation, yield and reliability.

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, power dissipation, fabrication yield, and reliability worsen steadily making further nanometric scaling increasingly difficult. These problems would stop further scaling of silicon-based CMOS technologies at channel lengths between 10 and 20 nm. But even before reaching these limits, these problems could become show-stoppers unless new techniques are introduced to maintain acceptable levels of power dissipation, yield and reliability. The paper describes the principles of GRAAL (global reliability architecture approach for logic), a new fault tolerant architecture for logic designs, aimed to provide a global solution for mitigating the above mentioned problems.

ISBN 0-7695-2566-0

This panel will bring together a set of experts working in a collaborative project to address at both experimental measurement and simulations all levels of the process leading to system failures induced by soft errors. Several aspects will be discussed, e.g. interaction between energetic particles and the matter, detailed analysis of transient pulse generation and propagation, dependence of the circuit topology and system architecture.

Single-event latchup is one of the most threatening single event effects as the induced current may destroy the affected device. Existing latchup mitigation schemes may induce a very high area cost or may require modifying the fabrication process. In this paper we present a new single-event latchup mitigation approach implemented at design level that protects devices from destruction and preserve circuit state at very low area cost

Three soft-error experts from industry will discuss the way their companies understand the impact of soft-errors on electronic systems, whether they consider soft-errors as an already existing or upcoming risk, whether they use or intent to introduce countermeasures and which are the best suited ones for their applications.

We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.

This special session includes a presentation on nuclear codes used to determine a data-base of secondary ion species and their energies produced by the neutron-silicon and neutron-oxygen interactions, a presentation on FIT estimation tools using the secondary ions data-base created by the former codes and a presentation on design techniques suitable for mitigating the effects of ionising particles on modern nanometric designs.

In this paper, the authors introduced an approach for single-word multiple-bit upsets (SMU) correction in SRAM. This approach uses the combination of built in current sensor (BICS) and Hamming single error correction/double error detection (SEC/DED) codes. The BICS is used with memory columns for online detection of upsets. When the upset is detected by the BICS, an immediate error correction is performed by the ECC. If ECC gives flag for uncorrectable error i.e. double or more errors in single word, then information from BICS is used to invert the data read from columns flagged by the BICS.

Various fault tolerant techniques can be employed to mitigate SEUs, SETs and SELs. However, such techniques usually inquire high hardware, speed and power penalty that most commercial applications could not afford. This presentation concerns low cost mitigation techniques for single-event effects induced by alpha particles and atmospheric neutrons in advanced nanometric designs.

In modern SoCs embedded memories include the large majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage. Fixing the test algorithm during the design phase may not be compatible with this goal, as thorough screening inspection or customer returns may discover after fabrication unexpected fault types. A programmable BIST approach allowing selecting after fabrication a vast variety of memory tests is therefore desirable, but may lead to unacceptable area cost. In this work we present a programmable memory BIST architecture offering such flexibility at an area cost similar to traditional memory BIST schemes

Memory built in self repair (BISR) is gaining importance since several years. New fault tolerance approaches are mandatory to cope with increasing defect levels affecting memories produced with current and upcoming nanometric CMOS process. This problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels that are several orders of magnitude higher than in current CMOS technologies. This work presents an evaluation of the area cost and yield of BISR architectures addressing memories affected by high defect densities. Statistical fault injection simulations were conducted on several memories. The obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost.

Memory built in self repair (BISR) is gaining importance since several years. Because defect densities are increasing with submicron scaling, more advanced solutions may be required for memories to be produced with the upcoming nanometric CMOS process generations. This problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels that are several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents a diversified repair approach merging ECC codes and self-repair, for repairing memories affected by high defect densities. The approach was validated by means of statistical fault injection simulations considering defect densities as high as 3*10/sup -2/% (3% of cells are defective). The obtained results show that the approach provides close to 100% memory yield, by means of reasonable hardware cost, for technologies of very poor quality. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories.

This paper presents memory built-in self-repair approaches allowing to achieve high yield for defect densities several orders of magnitude higher than in current technologies. Such repair schemes illustrate that we could build memories in nanoelectronic technologies that are subject to very high defect densities.

IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, they become increasingly sensitive to noise which result on unacceptable rates of soft-errors. Furthermore, defect behavior becomes increasingly complex, resulting on increasing numbers of timing and other spurious faults that can escape detection during fabrication testing. This makes increasingly difficult to achieve acceptable reliability levels for future ICs and maintain acceptable cost and quality for IC testing. One important reliability threat is related to single event transients (SET) and single-event upsets (SEU). An SEU is the consequence of a transient current pulse (single event transient), created when a particle strikes a sensitive node of an integrated circuit. When an SET occurring on a memory cell node flips the state of the cell it is transformed to an SEU. Similarly, when an SET occurring on a node of a logic network is propagated through the gates of the network and is captured by a latch as a logic error, it is transformed to an SEU. Atmospheric neutrons affect the operation of modern ICs even at ground level. A few years ago, the energy of the secondary particles produced by the nuclear reaction of neutrons with the matter of an IC was insufficient to affect its operation. However, as we approached 0.1um and use very low supply voltages, the rates of errors induced by cosmic neutrons became unacceptable. Furthermore, alpha particles produced by the disintegration of unstable isotopes of an IC material and its packaging, are another cause of increasing soft error rates. In addition in today technologies, soft errors concern not only memories (which was the case so far) but also logic. One basic reason for the increased sensitivity of logic parts is the reduction of the device size and the Vdd level. Since both the Vdd level and the circuit nodes capacitance Cnode are reduced, the charge stored on a node (Q = Vdd * Cnode) is reduced drastically. Consequently, a significantly lower charge deposed by a particle strike suffices to flip the logic value of a node creating a transient pulse (single event transient or SET), or to flip the state of a storage cell (single event upset). In the past, the probability of occurrence of a soft error in logic parts was drastically lower than in memories, due to the following reasons: (i) the propagation through logic gates can filter the induced transient pulse, and (ii) a transient pulse propagated through a logic network will result in a logic error only if it reaches the input of a latch simultaneously with the latching edge of the clock. For these reasons, traditionally, only memories have been protected against SEUs, even in a radiation hostile environment like space. Unfortunately, deeper submicron scaling increases drastically the sensitivity of logic networks too. In fact, a transient pulse wider than the logic transition time of a gate propagates through the gate without attenuation. Transient pulses induced by particle strikes have a width of a few hundreds of picoseconds (the exact value depends on the circuit characteristics and a particle’s energy). Since the transition time of logic gates is becoming very short in VDSM, the transient pulses cannot be attenuated even for relatively low energy particles. In addition, as the clock frequencies increase significantly, the probability of latching a transient pulse increases as well. Indeed, the more frequent are the latching edges of the clock, the higher is the probability to have a transient pulse coinciding with a latching edge. Due to these trends, the error rates in logic parts become significant. SETs and SEUs are not due to physical defects. circuit can perfectly work for the majority of the time but produce errors at random instances. Thus, we cannot use manufacturing (one-time) testing to cope with. As another problem, timing faults are gaining importance VDSM technologies. Process parameter variation and various defect types (shorts, opens...) often affect circuit speed. They increase signal delays and result on timing faults. They may require complex test conditions to be detected, due to the huge number of paths in modern ICs. In addition, some of these faults will be detected only if they are activated in conjunction with other timing critical conditions (e.g. cross talk, ground bounce, ...). This makes ATPG for such faults computationally unfeasible, and test length unrealistic. It becomes unavoidable that an increasing number of circuits with timing faults will pass fabrication tests. In this context, fault-tolerant IC design for soft errors and timing faults becomes mandatory for various application domains. Many of these domains cannot afford the high cost of fault tolerant schemes, such as TMR. Thus, alternative solutions are required. Fortunately, EDAC codes can protect memories at acceptable cost. For logic, the situation is more complex. However, due to the temporary nature of the targeted faults, concurrent error detection based on time redundancy, together with hardware retry mechanisms, can enable cost effective protection of logic. Such approaches will gain in importance in the near future. According to the ITRS roadmap, 1999 Ed., Design, p. 43): amongst Difficult Challenges in Systems Design (<100nm, beyond 2005) one can find: The ability to insert robustness automatically into the design will become a priority as the systems become too large to test functionally at manufacturing exit. automatic introduction of techniques such as redundant logic for fault tolerance is needed.

In this paper, we present efficient self-checking implementations valid for all existing adder and arithmetic and logic unit (ALU) schemes (e.g., ripple carry, carry lookahead, skip carry schemes). Among all the known self-checking adder and ALU designs, the parity prediction scheme has the advantage that it requires the minimum hardware overhead for the adder/ALU and the minimum hardware overhead for the other data-path blocks. It also has the advantage to be compatible with memory systems checked by parity codes. The drawback of this scheme is that it is not fault secure for single faults. The scheme proposed in this work has all the advantages of the parity prediction scheme. In addition, the new scheme is totally self-checking for single faults. Thus, the new scheme is substantially better than any other known solution.

Signal integrity has been pointed out as a major challenge. More and more causes can affect signal integrity as geometries are shrinking. One of the growing effects is the so-called "transient errors" which are due to temporary condition of use and environment. Cross-coupling, ground bounce, external terrestrial radiations create more and more unpredictable transient and soft errors which affect system reliability in unacceptable ways. In addition, reliability in devices like memories become a critical issue: the MTBF (mean time before failure) level decreasing the global system FIT (Failure in Time) rate approaching the critical border line for the end user. Hence, for memories and for logic blocks as well using high-end process technologies, self-correcting intelligence embedded in SoC is needed to enable electronic systems to react against unpredictable and insidious errors.

The following topics are dealt with: formal verification of designs; cooling layout; power analysis; SAT; BDD; interconnects; low power design; advanced mixed signal testing; collaborative design; logic synthesis; SoC; symbolic techniques; EDA tools; platform based design; analogue simulation; asynchronous circuits; BIST; network on chip; modelling; embedded systems; reconfigurable architectures; test resource partitioning; deep submicron design; logic synthesis; buffering; automatic design; object oriented systems; real time systems; online testing; fault tolerance; design space evaluation; architectural level synthesis; memory testing; high level synthesis; coupling and switching noise; and power optimisation.

Increased performance has been the key innovation in new products over the last few years. Market demand for this performance feature has helped make the semiconductor business quite profitable. Technology evolution has been driven steadily by more performance at a lower cost. To meet such time-to-market constraints functional IP has been leveraged because of its reusability feature. Approaching physical limits of silicon with a huge number of transistors threatens the manufacturability and usability of the final system on a chip (SoC). Yield, debugging, test and reliability are now more and more critical for SoC sign-off Infrastructure IPs enable designers to manage these challenges by detecting, analyzing and correcting defects or signal corruption. One specific domain where infrastructure IP brings a key value is robustness. Signal integrity is becoming more and more critical in VDSM chips, causing a new challenge that threatens information integrity, systems availability and security. Both consumer and business owners of electronic products will demand high reliability as a companion to performance. Downtime and ongoing service costs must be reduced or eliminated. We call this the Robustness Challenge.

IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable rates of soft-errors. Furthermore, defect behavior is becoming increasingly complex resulting in increasing number of timing faults that can escape detection by fabrication testing. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation and improvements of a new soft error and timing error detecting technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the approach. Simulations and performance evaluations of the proposed detection technique were made using time and logic simulators. The obtained results show that detection of such temporal faults can be achieved by means of meaningful hardware and performance cost.

IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise as well as to small manufacturing defects that may result in spurious faults. Such faults are difficult to (or can not) be detected by manufacturing testing and will result in unacceptable rates of errors in the field. Self-checking design can be used to cope with this problem, but usually it addresses logic faults. This paper analyzes the behavior of self-checking circuits under various spurious faults likely to occur in very deep submicron technologies.

Summary form only given. Progress in technological scaling allows the integration into a single chip of hundreds of millions of transistors, moving quickly to the multi-billion transistor capacities. Achieving acceptable quality and reliability levels for these complex products is one of the most critical issues that need to be faced. Testability is therefore a key factor that could limit these trends if not addressed adequately. At these levels of complexity external testing is becoming infeasible due to ATPG limitations. At the same time, the scan approach is losing interest due to the increasing length of scan chains (and thus test length), and low test application speed. At-speed test is a major limitation at a context where increasing clock frequencies (moving quickly to the multi-GHz domain), are making timing faults predominant. Automatic Test Equipment (ATE) is another important limitation, since, although its very high cost, it does not offer the memory capacities/depth and test application speed required for testing present day ICs. Under these constraints, the only realistic issue is to extend the BIST practice beyond memory testing. This requires new developments on logic BIST for increasing fault coverage while containing hardware cost. Furthermore, new developments on fault modeling, fault simulation, and ATPG tools are needed to encounter for timing faults, cross talk, ground bounce and other spurious faults. These developments should be oriented towards a BIST approach.

The basic drawbacks related to the design of self-checking circuits include high hardware cost and design effort. Recent developments on self-checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware cost in self-checking data paths for the majority of basic data path blocks such as, adders, ALUs, shifters, register files, etc. However, parity prediction self-checking multipliers involve hardware overhead significantly higher than for other blocks. Thus, large multipliers will increase significantly the hardware overhead of the whole data path. Residue arithmetic codes allow to reduce this cost The tools presented in this paper generate automatically self-checking multipliers using such codes. They complete our tools using parity prediction for various other blocks, and enable automatic generation of low cost self-checking data paths.

No abstract available.

In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are non-robustly testable and we give a path selection method so as all the selected paths to be robustly testable by 20*log/sub 2/n+2 test-vector pairs, where n is the length of the shifter. The propagation delay along all other paths is a function of the delays along the selected paths.

In this paper, we present a new online built-in self-test (BIST) approach for testing analog circuits. It uses a current window comparator and current-based checker circuits for processing the test response of the analog parts in mixed-signal integrated circuits. Online analog BIST capability is achieved by using high-speed current-mode circuits. A leapfrog filter has been considered as a test vehicle, and simulation results show the feasibility and effectiveness of the proposed BIST approach.

One way to improve reliability in parallel computers consists of adding supplementary processors and interconnections to the functional structure in order to replace faulty processors with respect to the network structure. This approach is named structural fault tolerance (SFT). Very integrated parallel computers are one way to implement a parallel structure. The material structure is then composed of many elementary blocks, such as ASICs or multi-chip modules (MCMs), each containing many processors. We show that former SFT methods fail in combining the different features, constraints and requirements of such structures. Thus, this paper introduces a new reconfiguration approach that is dedicated to very integrated parallel computers.

This paper describes results on Built-In Current Sensors (BICS) destined to overcome the limitations of I/sub DDQ/ testing in deep submicron circuits. The problems of performance penalty, test accuracy and test speed are addressed. A new sensor composed of a source-controlled comparator operating at low supply voltages and bias currents is used. Gradual sensor activation ensures reliable low noise operation. It is combined with large bypass MOS switches avoiding performance penalty, as well as a second bypass and compensation logic to increase test speed.

The increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling, affect the reliable operation of very deep submicron ICs. The effects of various noise sources are becoming of great concern. In particularly, it is predicted that single event upsets induced by alpha particles and cosmic radiation will become a cause of unacceptable error rates in future very deep submicron and nanometer technologies. This problem, concerning in the past more often parts used in space, will affect future ICs at sea level. This challenging problem has to be solved otherwise technological progress will be blocked soon. Thus, fault tolerant design is becoming necessary, even for commodity applications. But economic constraints of commodity applications exclude the use of traditional, high-cost fault tolerant techniques. This work uses time redundancy techniques to derive low cost soft-error tolerant implementations for logic networks.

A new digital BIST structure is proposed in this paper. During test mode, the op amp under test is placed in a voltage follower configuration in order to detect its slew-rate deviation, or in a comparator configuration in order to detect its signal propagation delay deviation. The test stimuli and the BIST control signals are simply derived from the test control signal TST using delay elements and logical gates. The test response is analyzed by using pure digital circuitry. Simulation results show the effectiveness of the proposed technique with a low area overhead.

A new approach for the on-line testing of operational amplifiers embedded into analog and mixed-signal circuits is presented in this paper. A built-in detector is used for providing an on-line test signal, which is suitable for concurrent error detection in operational amplifiers. The fault detection strategy is based on monitoring via an analog checker the normal output/input and the on-line signal of operational amplifiers. In this context, the circuitry associated with a self-checking operational amplifier is presented. In order to evaluate the fault coverage and the performance degradation in the resulting operational amplifier, extensive simulations are performed considering catastrophic faults.

The basic drawback of parity prediction arithmetic operators is that they may not be fault secure for single faults. In a recent work we have proposed a theory for achieving fault secure design for parity prediction multipliers and dividers. This paper has not considered the case of Booth multipliers using operand recoding. This case is analyzed here. Parity prediction logic and fault secure implementation for this scheme is derived.

A new test technique for linear analog circuits which employs current injection as input test stimulus is described. Our investigations have shown that current transitions resulting from a current injected on internal test points are significantly different for the fault free and faulty circuits. This can be used for fault detection purposes. In fact, the current injection as test input stimulus represents a powerful alternative to the test approaches based on conventional voltage input stimulus. The new approach allows one to improve the testability of various faults, which are difficult to detect or are untestable when using voltage-based test stimulus. In addition the technique has significant advantages for BIST purposes. The technique is illustrated by means of a modern opamp circuit and by considering catastrophic and gate-oxide-short (GOS) faults.

A new test technique for analog and mixed-signal circuits which employs current signals as input test stimuli is presented in this paper. With the current-based test technique proposed, it is possible to simplify test stimulus generation, minimize the probability of erroneous test decisions and maximize fault coverage. In addition, this technique has significant advantages for DFT and BIST implementations, since high controllability can be achieved for test stimulus application, and analog multiplexers are not required in the signal path of the analog system to apply the current-based test stimuli. The technique is illustrated by means of opamp circuits and analog filters, and by considering catastrophic and parametric faults.

Error detecting and correcting code based memory design, self-checking design, VLSI-level retry architectures, perturbation hardened design, tools for evaluation of soft error rates, and other on-line testing techniques are becoming mandatory in order to achieve increasingly levels of soft-error robustness and push aggressively the limits of technological scaling. In the next few years, considerable efforts have to be concentrated on the development of such techniques and the related CAD tools.

This paper presents the design of strongly fail-safe interfaces which transform binary signals, generated by a system with error detection capabilities and eventually with fault-tolerant capabilities, into fail-safe signals, that is to say, into signals which, in the presence of failures, will be either correct or safe. The strongly fail-safe property is achieved by means of concurrent checking techniques. The interest of these interfaces is that they can be implemented in VLSI, while the conventional fail-safe interfaces require using discrete components. A formal theory of fail-safe systems is developed to guide the implementation of the new solutions.

A large variety of on-line testing techniques for VLSI was developed in the past and are still enriched by new developments. They can respond efficiently to the increasing complexity of VLSI circuits under the condition that available CAD tools simplify their implementation. Amongst the advanced online testing techniques are: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test, ...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components, radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

This paper presents a new test pattern generation technique for complex systems. It focusses on test vector propagation through the individual blocks in the system. The technique is based on an easy identification of input-output pairs in each block. E (equality)-groups are formed for each block such that all the input vectors producing an identical output are grouped together. Such a grouping speeds up the task of backward propagation. In contrast to earlier methods, which considered the circuit structure for propagation, this method uses a functional approach and propagates the entire vector in one step. It is especially relevant to systems which consist of several blocks through which the test vector must be propagated. Results show that a significant reduction in the test generation time is possible.

Parity prediction arithmetic operator schemes have been widely studied in the past. Recently, it has been demonstrated that this prediction scheme can achieve Fault-Secureness in arithmetic circuits for stuck-at and stuck-open faults. In this paper it is shown that the detection capability improves if a current monitoring technique is used in conjunction with the parity prediction scheme. With this scheme the fault-secure property extends to bridging faults. The technique is validated by the topological design and SPICE simulation of a multiplier circuit.

I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a transparent one. The interest of the transparent test algorithms is that testing preserves the contents of the RAM. The transparent test algorithm is then used to implement a transparent BIST. This kind of BIST is very suitable for periodic testing of RAMs. The theoretical analysis shows that this transparent BIST technique does not decrease the fault coverage for modeled faults, it behaves better for unmodeled ones and does not increase the aliasing with respect to the initial test algorithm. Furthermore, transparent BIST involves only slightly higher area overhead with respect to standard BIST. Thus, transparent BIST becomes more attractive than standard BIST since it can be used for both fabrication testing and periodic testing.

Several systematic design approaches are known to be representatives of the techniques well adapted for testing sequential circuits (partial and full scan, LSSD...). However in some cases, like for the test of on-line operators, ad-hoc DFT (design for testability) schemes become more suitable. Indeed, on-line arithmetic are used for high precision numbers resulting on high length operators. Thus the length of a test sequence for a scan design approach can grow quite large due to the shift in (shift out) of test values (test responses) and therefore the test application time would become prohibitive. Moreover, the arithmetic nature of these operators imply that some errors detected locally are masked before their observation at the primary outputs. In this paper we describe an analytic approach for testing on-line multipliers that allows to avoid error masking without adding extra hardware for internal state observability while maintaining a 100% fault coverage. Compared to a DFT approach using parity trees, this method leads to a reduction of the area overhead from 7% to 1% and of the extra pins count from 6 to 3 in the case of the on-line multipliers considered in this paper.>

This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction.

In this paper we illustrate that exact aliasing computation in RAM BIST can be achieved with respect to accurate RAM fault models including single and multiple stuck-at, transition and coupling cell-array faults and decoder stuck-at faults.

This paper presents a new technique for designing reliable multichip modules (MCMs) under radiation effects for spacecraft electronics. The technique is based on current monitoring to detect faults induced by ionizing radiation in dies mounted on the MCM. These faults change transistor electrical parameters and increase power consumption due to increased leakage current. In addition to this fundamental benefit, the proposed approach can also be used to assess product quality during manufacturing testing.

An important drawback of implementing self-checking circuits concerns the lack of dedicated CAD tools. This problem results on a significant increasing of the design effort and compromises the interest of such designs. CAD tools aimed to implement self-checking data paths is of high interest since data-paths are basic parts of microprocessors and microcontrollers. The tools presented here include generators of self-checking adders, ALUs, multipliers, dividers, shifters and register files, as well as generators of parity and double rail checkers. Another tool interconnects these blocks to generate the self-checking data-path.

We present a strongly code disjoint (SCD) built-in current sensor (BICS) based on self-exercising concept. The integration of this SCD BICS with a self-checking circuit achieves the totally self-checking goal in static CMOS realizations, even in the presence of stuck-on and bridging faults, and results in a strongly fault-secure realization. Low-cost and high fault coverage is attractive for many high reliability and critical applications.>

In this paper, the effects of simultaneous write access on the fault modeling of multiport RAMs are investigated. New fault models representing more accurately the actual faults in such memories are then defined. Subsequently, a general algorithm that ensures the detection of all faults belonging to the new fault model is proposed. Unfortunately, the obtained algorithms are of O(n/sup 2/) complexity which is not practical for real purposes. In order to reduce the complexity of the former test algorithm a topological approach has been developed. Finally, a BIST implementation of one of the proposed topological algorithms is presented.>

Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, we fake advantage from the regularity of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST.

This paper deals with the test of an integrated on-line multiplier suitable for very large numbers. Due to the serial structure of the circuit, the controllability and observability of the different elements are very low. In particular, an embedded sequential array cannot be accessed directly and has no primary outputs. Therefore, we propose here two DFT alternatives. The first one determines the most significant nodes to be considered in order to avoid error masking. The second approach increases the parallelism of the circuit and presents, thus, the advantage of a large reduction in the test duration. Both options have a low area overhead and a reduced number of extra pins.>

First presents a self-checking implementation for RAMs. Then, the unified BIST technique is applied to this scheme. It merges self-checking and BIST techniques and allows a high fault coverage for all tests needed for integrated circuits, e.g. off-line test (manufacturing and maintenance test) and periodic as well as concurrent on-line testing. In order to preserve the RAM contents for periodic on-line testing the authors employ a transparent BIST implementation.>

The final checker of a self-checking system is an embedded double-rail checker (the partial checkers have in general two outputs). The self-testing or the strongly code disjoint property of this embedded checker can be lost if it is not exercised by an appropriate set of inputs. If some partial checkers are strongly code disjoint, then some undetectable faults can modify the input/output mapping of these checkers. This can compromise the exercising of the final double-rail checker especially if this modification leads to the reduction of the partial checker's output code space. In that case it will be required that the partial strongly code disjoint checkers must also be strongly fault secure. In this work we show that the (two-output) strongly code disjoint checkers do not allow such reduction of their output code space and on this basis we show that the strongly fault secure property is not necessary. We also give some techniques that ensure exercising the final checker.>

This paper presents a study of the behavior of a built-in current sensor (BICS) to be used for online concurrent error detection in circuits working in radiation-exposed environments. BIC sensors are used to monitor the power-bus static current of these circuits to detect excessive current consumption. This excessive static current consumption is compared to a predefined reference value in order to detect radiation-induced multiple parametric failures and system power supply breakdown. BIC sensors can also be affected by these faults and the reliability of the system can be lost. However, we show that the proposed current sensor is strongly code disjoint (SCD) with respect to the above faults and the system reliability is guaranteed.>

The theory of digital self-checking circuits has been developed in order to make formal the techniques of designing digital circuits allowing one to ensure on-line concurrent error detection. In recent years analog and mixed signal circuits have gained importance and represent a relevant part of the products of the integrated circuits industry. The design of self-checking analog and mixed signals circuits is a potential solution in order to achieve the reliability of systems using such circuits. Thus, establishing the self-checking theory for analog and mixed signal circuits will allow one to make the design of such circuits formal, and is of great importance. This paper proposes the basic theory of self-checking analog and mixed signal circuits and applies this theory to the case of current checkers which should become in the future an important element for high quality manufacturing, testing and on-line concurrent error detection.>

Presents a novel approach to estimate the I/sub ddq/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, the approach proposes the characterization of the quiescent current by evaluating the minimal power-bus current corresponding to an output voltage range characterized by the designer to be defective. This output voltage is defined by the designer in order to meet some desirable quality requirements for the circuit on the design, for instance, minimum acceptable noise immunity and maximum time delay. For the design of built-in current sensors, these quality requirements define the minimum current resolution. This approach is exemplified with the characterization of an in-house developed cell library.>

An efficient BIST architecture for RAMs that is based on M. Marinescu's (1982) algorithm is presented. This architecture considers the different levels of hierarchy of the algorithm and uses a block to implement each level of this hierarchy. Efficient implementations for these blocks are given. A transparent BIST technique, i.e., a BIST technique that preserves the initial contents of the RAM, is also presented, and an efficient transparent BIST architecture for RAMs is proposed. A tool allowing the automatic generation of BISTed and transparent BISTed RAMs is given. This generator is developed around the CADENCE CAD tools and uses the ES2 SOLO2030 standard cell library (CMOS 1.2 mu m).>

The author shows that, if the number of the states of the reduced flow table of an iterative logic array (ILA) is not a power of 2, then, the truth table verification of the ILA requires to test it exhaustively. Thus, in this case the theory presented by F.J.O. Dias (1976) and allowing the truth table verification of ILAs by means of C-tests, is not valid. Then the author extends this theory to the case where the ILA cells have some inputs in common (such ILAs are for instance ALUs, and the rows of multiply and divide arrays).>

A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed.>

The authors present a novel approach to the test of multi-port RAMs. A novel fault model that takes into account complex couplings resulting from simultaneous access of memory cells is used in order to ensure a very high fault coverage. A novel algorithm for the test of dual-port memories is detailed. This algorithm achieves O(n) complexity thanks to the use of some topological restrictions. The authors also present a novel built-in self-test (BIST) scheme, based on programmable schematic generators, that allows great flexibility for ASIC (application-specific integrated circuit) design.>

Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is that they involve a significant increasing of the circuit area. Recent experiments on Berger code encoded programmable logic arrays (PLAs) result in 46.9% average area overhead. In order to decrease this overhead, some other self-checking PLA implementations based on the Berger code are proposed. The tool allowing the generation of the conventional Berger code coded PLAs is modified to perform the new implementations. Experiments on the same set of PLAs show that the new implementations reduce the average area overhead from 46.9% to 20.1%.>

An improved self-checking solution for the sequencing part of the MC 68000 microprocessor is presented. Compared with previous self-checking schemes for this microprocessor, the present scheme makes its possible to reduce the overhead and simplifies the implementation of both functional circuits, and checkers. The unified BIST (built-in self-test) method is applied to this scheme. This method uses a merging of self-checking and BIST techniques and allows a high fault coverage for all tests needed for integrated circuits, e.g., offline test (design verification, manufacturing, and maintenance test) and online concurrent error detection. An area overhead of about 27% is required, which is quite satisfactory in comparison with previous results.>

An original built-in self-test (BIST) scheme is proposed aimed at covering some of the shortcomings of self-checking circuits and applicable to all tests needed for integrated circuits. In this scheme, self-checking techniques and built-in self-test techniques are combined in an original way to take advantage of each other. The result is a unified BIST scheme (UBIST), allowing high fault coverage for all tests needed for integrated circuits, e.g., offline test (design verification, manufacturing test, maintenance test) and online concurrent error detection. An important concept introduced is that of self-exercising checkers. The strongly code-disjoint property of the checkers is ensured for a very large class of fault hypotheses by internal test pattern generation, and the design of the checkers is simplified.>

The authors describe a design-for-testability strategy for the SYCO control section compiler (CPC). The SYCO CPC translates high-level descriptions into mask-level specification for hierarchical control sections, which are composed of a stack of control section slices, each one organized around a programmable logic array. The proposed design-for-testability scheme is called UBIST (unified built-in self-test) and ensures a high quality for all tests needed for integrated circuits (i.e. online and offline tests). The authors elucidate the concept of UBIST and show how to modify SYCO CPC data structure and its automatic layout synthesizer to generate UBIST control sections automatically and efficiently.>

Strongly code-disjoint (SCD) checkers are defined and shown to include totally self-checking (TSC) code-disjoint checkers. This type of checker is the natural companion of strongly fault-secure (SFS) networks. SCD checkers are the largest class of checkers with which a combinational system may achieve the TSC goal. Some examples are given to illustrate the design of SCD checkers.>