Summary form only given. As VLSI technology advances, it forces changes in the business organization of the industry. Traditional vertically integrated semiconductor manufacturers are concentrating less on manufacturing as foundries such as TSMC, UMC, and Chartered grow. These foundries supply capacity not only to fables houses but also to even large semiconductor manufacturers. As a result, these semiconductor houses are spending more time creating novel platforms for important applications. This puts them in competition with the systems houses that traditionally were their customers.

This paper gives an overview on a virtual electronic component or IP (Intellectual Property) exchange infrastructure whose main components are a XML "well structured IP e-catalog Builder/spl trade/" and a " XML IP profiler/spl trade/." While the first module is an e-publishing and an exchange management module, the second has as a role the extraction from the design directories the IP files and to trigger their transfer to the user site possibly via an IP distribution server under the catalog control. Direct design file extraction from commercial configuration systems such as CVS and Clearcase is supported. Also it is pointed out that the architecture supports, if required, a network of IP distribution servers to prevent a performance bottleneck when exchanging IPs; both modules have been implemented respectively in Java Servlet and as a Java client/server application.

This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed by Kuznar et al. (1995), but instead of using the replication and re-optimization, it takes force of the classical iterative improvement partitioning techniques. The basic effort consists in guiding the classical algorithms in their solution space exploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solution and carefully tuning the basic parameters of the classical algorithms such as definition of size constraints for feasible moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results comparable to the best published results, and even outperforms them for the largest benchmarks.

No abstract available.

No abstract available.

The goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. The circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. The floorplanning is then guided b y this cone structuring and has two innov ativ e features:first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, th us a significant reduction is obtained; second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.

Circuit designers and high-level synthesis tools have traditionally used circuit hierarchy to partition circuits into packages. However hierarchical partitioning can not be easily performed if hierarchical blocks have too large a size or too many I-Os. This problem becomes more frequent with field-programmable gate arrays (FPGAs) which commonly have small size limits and up to ten times smaller I-O pin limits. An I-O bottleneck often occurs which during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. More critical timing paths between packages are cut and circuit operational frequencies are drastically reduced. In this paper, two new partitioning algorithms are presented that use cone structures to partition large hierarchical blocks into FPGA's. Cone structures are minimum cut partitioning structures for netlists with low fanout, and clustering structures for partitioning netlists with high fanout. Cone structures also allow for full containment of critical paths. When used with good merging and cutting strategies, results show the cone partitioning algorithms given here produces fewer FPGG partitions than min-cut with good performance.

This paper addresses an automatic partitioning method of adesign into several FPGAs. Although the circuit partitioningmethods have recently been significantly advanced, partitioningis commonly performed at the gate netlist level. To cope withlarge designs and explore the solution space efficiently,clustering of the logic is mandatory. In this paper, the hierarchyof the design, naturally introduced by the designer, guides thepartitioning. The basic concepts are introduced in terms of"envelope" delimiting hierarchy blocks. These concepts lead toan "envelope"-based clustering and to the proposed finalhierarchy-driven partitioning. Results are given on industrialexamples on XILINX 4000 technology.

Because the VLSI circuits complexity growth, the trend in design is towards divide-and-conquer schemes, in which circuits are composed of blocks, standard macros or custom macros. From the other side, to allow an implementation of large digital circuits, increased capacity target FPGAs are organized hierarchically. In this paper, we present a hierarchical FPGA floorplanning method which takes into account both the hierarchy of the design and the hierarchy of the target. The method aims at minimization the timing and balancing cost of the floorplan and is based on automatic detection of macro blocks and assigning them to the target FPGA hierarchical zones.

No abstract available.

This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated. The approaches employed for achieving the goal of yield enhancement in the data path and the control part of the microprocessor are described first. Then, the yield enhancement due to the incorporated redundancy is analyzed. Finally, some practical and theoretical conclusions are drawn.>

Circuit partitioning for packages that have limited numbers of IO pins is a critical problem with FPGAs. Common FPGAs have prespecified maximum gate count limits on the order of five to ten times the number of usable IO pins. Traditional min-cut approaches lack the ability to find such constrained partitions with high gate to IO pin ratios. In this paper, a new partitioning algorithm is presented that uses cone structures. Cone structures are minimum cut partitioning structures for netlists with low fanout, and clustering structures for partitioning netlists with high fanout. Cone structures also allow for full containment of critical paths. When used with good Merging/Cutting strategies, results show that the cone partitioning algorithms introduced here produce better partitions than min-cut.

Signature analysis is often used in the test area to reduce the amount of information to check. The drawback of this compaction is its non-zero aliasing probability, i.e. the possibility to obtain a correct signature in spite of errors in the compacted words. Up to now, the studies on aliasing have focused on BIST applications and do not consider correlations between errors in two compacted words. However, online test methods also use signature analysis. The reported experiments show that, in this context and for some types of faults, the existing correlations have a noticeable impact on the aliasing probability. Further theoretical studies taking into account these correlations are therefore required to model the aliasing observed at each compaction step. It also seems that checking a signature in the middle of a linear block of instructions is better than checking it just before or after a branching instruction.>

A synthesis approach for a set of Boolean functions on table-lookup-based field programmable gate arrays is proposed. Synthesis is considered as a global problem and, therefore, includes suitable factorization techniques as well as decomposition methods relying on the factored form. The factorization step looks for lexicographical expressions of Boolean functions. Some trade-offs between a strict input-driven decomposition and a maximal cell filling strategy are presented. The approach is applied to the Xilinx XC3000 and XC4000 series. Decomposition techniques both for area and speed optimization are detailed and their performance is compared to all available performance results.>

This paper proposes a new type of expression for Boolean functions called lexicographical expressions. The basic idea is to impose an input ordering for factoring logical expressions. Several algebraic properties are presented and relations with classical algebraic theory are established. The main result is that all elementary factorizations defined by (Cokernel, Kernel) pairs "compatible" with an input order are all "algebraically compatible," i.e., are all parts of a single factorization of the function. Thus for a given input order a unique factorization is defined. This leads to fast division procedures. Basic techniques for obtaining lexicographical factorizations are presented. First, a precedence matrix and an updating procedure are defined and used later to select an input order and a corresponding compatible factorization. Second, a factorization technique respecting a fixed order is detailed. This method is then applied to multilevel synthesis using standard cells which was the original motivation of this work. The goal is to reduce wiring complexity. A lexicographical factorization leads to a wiring area reduction due to the structuring of the logic into layers in which the inputs enter the layout in the order given by the factorization. Experimental results comparing this approach to classical ones are given. These results include routing ratio measurements, routing structure observation, global area measurement and critical path estimation. All these results are analyzed after place and route, using an industrial tool (COMPASS Design Automation tool).>

Synthesis methods are presented for multiplexer-based field-programmable gate arrays, (FPGAs) based on binary decision diagrams (BDDs) for speed optimization, and reduced ordered binary decision diagrams (ROBDDs) for area optimization. A direct mapping is performed on the two types of binary decision diagrams. Practical results are given for an exhaustive list of benchmarks. The results show a big improvement compared to library based approaches.>

Article Free Access Share on A technology mapping method based on perfect and semi-perfect matchings Authors: M. Crastes Institut National Polytechnique de Grenoble/CSI, 46 Av. F. Viallet 38031 GRENOBLE Cedex, France Institut National Polytechnique de Grenoble/CSI, 46 Av. F. Viallet 38031 GRENOBLE Cedex, FranceView Profile , K. Sakouti Institut National Polytechnique de Grenoble/CSI, 46 Av. F. Viallet 38031 GRENOBLE Cedex, France Institut National Polytechnique de Grenoble/CSI, 46 Av. F. Viallet 38031 GRENOBLE Cedex, FranceView Profile , G. Saucier Institut National Polytechnique de Grenoble/CSI, 46 Av. F. Viallet 38031 GRENOBLE Cedex, France Institut National Polytechnique de Grenoble/CSI, 46 Av. F. Viallet 38031 GRENOBLE Cedex, FranceView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 93–98https://doi.org/10.1145/127601.127634Published:01 June 1991Publication History 8citation165DownloadsMetricsTotal Citations8Total Downloads165Last 12 Months7Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A state assignment method is described. The first step of this method recognizes predictive minimization situations in the control flow graph. It is based on the partition pair theory and privileges the cube collapsing in the next state and output equations with regard to factorization. The second step uses a powerful intersecting face embedding theory in the Boolean lattice. This approach has been implemented by software in the ASYL system, and tested on official as well as industrial examples. The gain in silicon area, critical path, and routing factor with respect to random assignment appears to be the best presently known.>

This paper focuses on the adaptation of a concurrent control-flow checking technique to pipelined RISC microprocessors. This technique, called embedded signature monitoring (ESM), verifies the validity of the instructions executed by the processor. Numerous ESM schemes have been studied with non pipelined processors but up-to-date machines pose new problems. The instruction pipeline of these processors makes difficult to know which instructions are actually executed among the fetched ones: the pipeline may be flushed when a jlowcontrol instruction is executed or when an exception is taken. A behavioural model is presented for the pipeline of most recent processors. It is used to propose a new simple ESM scheme compatible with these processors. This scheme is experienced on the Motorola MC88100 RISC processor. The design of a signature monitor dedicated to this processor is presented and hardware costs are discussed.

A hierarchical test generation method is presented which is based on a functional approach to guide backward and forward propagations. The proposed algorithm permits solving most propagation conflicts by taking advantage of the functionality of the implemented block and avoids costly unnecessary design modifications. It has been implemented and its effectiveness has been proved on a set of datapaths. The formalism and the algorithms are general enough to handle any type of synchronous digital circuit.

A multilevel logic synthesis method based on standard cells and aiming at reducing both gate and wiring areas is presented. The goal is to decrease the routing factor which is defined as a ratio between the routing area and the gate area. The wiring is taken into account during the synthesis steps (factorization and technology mapping). The approach is based on a lexicographical expression of a Boolean function controlling the input dependency and on a kernel filtering controlling the excessive factorizations responsible for wiring complexity increase. >

A distributed, synchronous architecture for artificial neural networks is proposed. A basic processor is associated to a neuron and is able to perform autonomously all the steps of the learning and the relaxation phases. Data circulation is implemented by shifting techniques. Customization of the network is done by setting identification data in dedicated memory elements. The neuron has been implemented on silicon. It is shown that, in a silicon compiler environment, dedicated networks can be easily generated by cascading these elementary blocks

A method for introducing online test facilities in a controller with a very low overhead is presented. This online test consists of detecting illegal paths in the control flow graph. These illegal paths may be due either to permanent faults or to transient errors. The state code flow is compacted through polynomial division. An implicit justifying signature method is applied at the state code level and ensures identical signatures before each join mode of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison to reference data is greatly facilitated. This property is obtained by a state assignment, nearly without area overhead. The controllers can then be checked by signature analysis, either by a built-in monitor or by an external checker.>

The controller state assignment methodology proposed here features two improvements over existing methods. First, a larger set of predictive minimizations in the control flowgraph is performed. Secondly, the embedding phase uses a new theory of intersecting cubes in the Boolean lattice. Practical results using the VLSI Technology Logic-Synthesizer on both PLA and multi-level logic demonstrate the effectiveness of the approach.

A novel method for introducing online test facilities in a controller with a very low overhead is presented. This online test consists of detecting illegal paths in the control flow graph. These illegal paths may be due to either permanent faults or transient errors. The implementation of the detection facilities relies on a clever choice of the state codes of the controller, which can then be checked by signature analysis by either a built-in monitor or an external checker.>

A distributed, synchronous architecture for neural networks is presented. The basic processor is associated to one neuron and is able to autonomously perform all the steps of the learning and relaxation phases. Data circulation is implemented by shifting techniques. Customization of the network is done by fixing identification data in dedicated memory elements.>

A novel method for optimized multilevel synthesis of CMOS circuitry in terms of compiled cells is presented. A compiled cell is the implementation on silicon of a lexicographical factorized Boolean expression. How a compiled cell is obtained automatically from the Boolean expression (layout synthesis) is recalled, and the rewriting of Boolean functions in terms of compiled cells is addressed. This approach leads to a dense and regular layout by abutment of compiled cells. The wiring channels are thus suppressed.>

The authors present a novel synthesis method of dedicated controllers which aims at the detection of faults which cause errors in the state sequences. The state code flow is compacted through polynomial division. An implicit 'justifying signature' method is applied at the state code level and ensures identical signatures before each join node of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison with reference data is greatly facilitated. This property is obtained by a clever state assignment, nearly without area overhead. The controllers can therefore be checked by signature analysis, either by a built-in monitor or by an external checker. The software implementation of the synthesis tool is presented, and the hardware implementation of the concurrent checking is described.>

The testability expertise of boards and ASICs (application-specific integrated circuits) relies on high-level models in the Prolog language. This high-level modeling makes it possible to describe chip and board functions at an adequate level of accuracy without giving useless details. Each chip is successfully considered as a test goal; difficult chips are identified. Design modifications in terms of multiplexers or scan path insertion are proposed according to a test strategy. As a final result of this analysis, the test planning (test data flow and test control, test scheduling) is defined. The resulting test program skeleton is then formatted to lead to the final test program.>

A design method using both logical optimization and optimized topological arrangements is described. Starting from a minimized Boolean function, a synthesis of an optimized well-structured network is obtained. The most original aspect of this approach is a transistor merging procedure leading to a nonseries-parallel network while maintaining a systematic layout. An extension to the synthesis of several functions relies on transistor mergings between functions and allows comparisons with a PLA implementation. Gains in both area and performance are obtained.>

This paper presents an advisory tool for fast cost estimation of floorplans made up of rectangular arbitrarily-sized building blocks. Emphasis is laid on efficient computer processing of available data. The floorplan information is translated into proximity matrices. Exploratory data analysis, based on a multivariate statistical approach, is used with a view to revealing patterns inherent in the data. The resultant patterns are then converted into metric representations.

A rule-based approach has been investigated for two items of the synthesis area: the state assignment of controllers and the logic minimization. Local optimization rules defined on a control flowgraph have been defined for the first point. These are expressed as constraints on the codes of the internal variables. An encoding algorithm tries to respect most of these contraints. The results appeared to be very convincing. For the second point, the rules intend to cope with different technological targets and the meta rules intend to express different optimization strategies. The results are less spectacular, especially, of course, for a target where algorithmic solutions exist, but some interesting experiences on the rule-based approach are reported.

The logical synthesis methods are dependant technology and must be strongly connected to the topological design. We present here a logical and topological synthesis method for complex MOS cells leading to a systematic, optimized and easy to interconnect layout.

A top down design methodology of VLSI Circuits used at the University of Grenoble is briefly presented. The choice of a data path is analyzed with respect to testability and diagnosability requirements. Design modifications (in terms of special test control) help achieves the testability requirements. Such an approach helps to avoid costly techniques like additional scan pathes (LSSD, Bilbo) Combined with dynamic analysis techniques (Stroboscopic analysis), this approach produces efficient VLSI tests.

This paper presents an automatic generation system for behavioral test programs of microprocessors. First, the test environment is presented, as well as its consequences on test program generation. In the second part, the test principles are outlined; it is a behavioral test, i.e a test determined from the user's description of the microprocessor; the resulting test programs are quite modular. The third part presents the description language and the generation system.

This paper deals with the protection of a dedicated subsystem against an erroneous environment. The inputs of the subsystem can be erroneous and the subsystem must be able to detect erroneous inputs and to recover from them.

The goal of the paper is to propose test methods for wired or microprogrammed control units without special test facilities: no special access path, i.e., no direct and exhaustive observation means. Consequently, the control unit will be tested through the current control algorithms under "normal" sequencing facilities and through the controlled operative part; the proposed methodology consists of choosing an adequate set of algorithms and specific data, allowing an efficient test with respect to errors hypothesis.

We suggest a methodology and a language to permit the study of a system's behavior (functional validation, evaluation of global performances, critical situations). Every system is regarded as an interconnection of communicating modules functioning in a synchronous or asynchronous manner. The control section and the data section of each module are described separately in terms of respectively non-procedural and procedural sub-languages.

Our purpose is to define a methodology for writing (micro) programs to test CPU's for which no or few test facilities are available.

Two different test methods, specific to two control mechanisms in a logic network are presented. These methods, in fact, correspond to two levels of complexity and therefore to two kinds of hardware realizations. The main considerations will be the following.

A new algorithm for asynchronous machines is presented. The problem is formulated and solved in graph-theoretic terms. A graph-embedding algorithm in an n-cube developed in Sections I-III is used to establish the encoding method. The resulting critical race free encoding minimizes the dimensions of the internal variables and the transition times. This method should be especially interesting for large incomplete machines.

A theorem and two applications are given here to solve the problem of selecting state assignments of asynchronous machines. The assignment has to produce a set of simple next-state equations. The proofs use the algebraic structures defined by Hartmanis. A first illustration is given by Liu's encoding; likewise, Tracey's selection theorems are easily found again and placed in a more general context.

This paper is intended to improve Huffman's results on universal encoding of asynchronous sequential networks. The method employed here consists of assigning to each row of the flow table a single vertex on the corresponding hypercube. The remaining vertices are used for the transitions between stable states. Such a vertex can be used for different transitions if they correspond to distinct input states. In order to verify that an assignment is universal, we have to generate all possible structures of columns (all partitions of the set of vertices assigned to the rows). Then, we have to verify that the chosen assignment is compatible with all these partitions. An assignment will be compatible with the structure of a column if 1) the elements of a block are connected by transient sequences of adjacent values of the internal variable; 2) the transient sequences of two distinct blocks have no common element. Interesting solutions that cannot be further improved are found for 7- and 8-row flow tables. For 12-row flow tables the use of a computer is indispensable. A solution of 5 components of the internal variable is proposed.