This paper describes a variation-robust transceiver with four-tap feed-forward equalization (FFE) and real-time calibration techniques. The design adopts the common-mode balanced and robust FFE (CMBB-FFE), which improves the previous current-mode coefficient-error-robust FFE (B-FFE) to achieve the consistent common-mode level across data patterns and support voltage mode operation. The real-time receiver calibration method adjusts sampling threshold voltages and clock phases in the middle of normal link operation, to enhance the sampling margin under dynamic drifting conditions. The transceiver test chip is fabricated in a 28-nm CMOS process. It occupies 0.419 mm$^{\mathbf {2}}$, achieving 20 Gb/s with 9.82-pJ /bit energy efficiency and 33.3% wider horizontal eye-opening by adopting the CMBB-FFE and real-time calibration techniques.

This article presents a method for extracting a channel thermal noise (Sid) using analytical equations and measured noise parameters. Among the four noise parameters considered (Rn, Gopt, Bopt, and NFmin), the equations of Rn and NFmin were used to extract Sid, since the Sid extracted from Gopt and Bopt was affected more by measurement variations. NTNOI, the noise enhancement factor of the charge-based thermal model of a Berkeley short-channel IGFET model 4 (BSIM4), was modeled as a gate-bias-dependent function to reproduce Sid extracted from the measured noise parameters. Regarding the accuracy of the proposed model, while the error rate was found to vary slightly depending on the device dimensions (finger number), the new model showed only 4% error for rn, compared to the default model's error of 41% obtained with NTNOI fixed at 1. In addition, the accuracy of Gopt, Bopt, and NFmin is substantially higher than that of the default model. Finally, the modeling technique using the holistic model, another BSIM4 thermal noise model, was briefly discussed.

The present work focuses on reducing dropout voltage and noise by exploiting the unique advantages of a complementary silicon-germanium (SiGe) heterojunction bipolar transistor (C-SiGe HBT) on SOI technology. We also explore the impact of utilizing different PNP device types on regulator performance. Design challenges arose from the off-chip load capacitor required to meet the specification of the instantaneous peak output voltage drop. To overcome these challenges, a right-hand plane (RHP) to left-hand plane (LHP) zero conversion technique with a nulling Miller resistor was applied. The complete solutions for the locations of the converted left-hand plane zero and the Miller pole affected by the nulling resistor were derived utilizing signal flow graphs without any assumptions commonly made in the literature. Two C-SiGe LDO regulators with two different types of PNP output devices were fabricated utilizing a commercially-available C-SiGe on SOI technology, and compared with the literature.

This paper introduces a systematic methodology for applying Mason's signal flow graph to the analysis of feedback circuits. We demonstrate that the relationships among signals of feedback circuits can be represented in a intuitive and graphical manner utilizing signal flow graphs. Once constructed, the desired solutions can be achieved by simple inspection of the signal flow graph. The Thevenin and Norton equivalent circuits are utilized to model the loading effects of the feedback network in the example circuits presented.