Single Event Transients (SET) in digital logic pose an ever increasing reliability challenge as device dimensions shrink in modern technologies. Projection of SET sensitivity with scaling is essential to assess the logic failure and error probability in modern technology generations. This paper discusses the effects of device scaling from 45nm to 12nm processes and circuit parameter tuning on SETs. The failure due to particle strikes i.e., Single Event upsets (SEU) as well as its behavior with process variations and reliability mechanisms such as NBTI is evaluated in this work. The critical supply voltage required to avoid SET propagation with circuit parameters is investigated. This work also proposes a probability model which examines the propagation of SET at any node to the output of a circuit. The proposed methodology can be extended to any complex digital circuit to investigate its vulnerability to SET.

Prognostics and health management enables in-situ assessment of a product’s performance degradation and deviation from an expected normal operating condition. A unique hybrid prognostics and health management methodology combining both data-driven and physics-of-failure models is proposed for fault diagnosis and life prediction. The shortcomings of using data-driven and physics-of-failure methodologies independently are discussed. These approaches estimate future system health, based on a systems current health status, historical performance, and operating environmental conditions. Although these methodologies are applicable to legacy, current, and future electronics, and ranging from components to circuit assemblies and electronic products, the hybrid approach is preferred due to its capability to include potential failure precursor parameters with failure mechanism, thus improving accuracy in prognostic estimates. Various works on data-driven and physics-of-failure approaches to prognostics for electronics are summarized and a hybrid methodology case study is presented.