Power gating is a widely used leakage power saving strategy in modern chip designs. However, power gating introduces unique power integrity issues and trade-offs between switching and rush current (wake-up) supply noises. At the same time, the amount of power saving intrinsically trades off with power integrity. In addition, these trade-offs significantly vary with supply voltage. In this article, we propose systemic decoupling capacitors (decaps) optimization strategies that optimally trade-off between power integrity and leakage saving. Specially, new global decap and reroutable decap design concepts are proposed to relax the tight interaction between power integrity and leakage saving of power gated PDNs with a single supply voltage level. Furthermore, we propose a flexible decap allocation technique to deal with the design trade-offs under multiple supply voltage levels. The proposed strategies are implemented in an automatic design flow for choosing the optimal amount of local decaps, global decaps and reroutable decaps. The conducted experiments demonstrate that leakage saving can be increased significantly compared with the conventional PDN design approach with a single supply voltage level using the proposed techniques without jeopardizing power integrity. For PDN designs operating at two supply voltage levels, the optimal performance is achieved at each voltage level.

Power gating is essential for controlling leakage power dissipation of modern chip designs. However, power gating introduces unique power delivery integrity issues and tradeoffs between switching and rush current (wake-up) supply noises. In addition, in power-gated power delivery networks (PDNs), the amount of power saving intrinsically trades off with power integrity. In this paper, we propose systemic decoupling capacitance optimization strategies that optimally balance between switching and rush current noises, and tradeoff between power integrity and wake-up time, hence power saving. Furthermore, we propose a novel re-routable decoupling capacitance concept to break the tight interaction between power integrity and power saving, providing further improved tradeoffs between the two. Our design strategies have been implemented in a simulation-based optimization flow and the conducted experimental results have demonstrated significant improvement on leakage power saving through the presented techniques.

Large VLSI on-chip power delivery networks (PDN) are challenging to analyze due to sheer network complexity. In this paper, three power grid solvers developed in our group: a direct solver using Cholesky decomposition, a GPU-based multigrid preconditioning solver, and a partitioning-based solver using spatial locality, are reviewed. Following the requirements of TAU 2011 Power Grid Simulation Contest, single-threaded versions of these solvers are implemented and their performances are evaluated in terms of runtime, memory, maximum error and average error. The experimental results show that for the published IBM power grid benchmarks, the direct solver has the best overall performance among the three.