The resource management (RM) of heterogeneous hardware cores within the large-scale embedded systems have been one of the key implementation and research subjects in last years. In future systems, consisting of growing number of heterogeneous hardware cores, the RM have to be implemented to control the energy drain, exploit maximally the performance potential, and also to improve robustness of the system by bypassing failing components. We present the resource management providing an API for parallel execution of operations on a heterogeneous set of resources. The RM controls the tasks execution and monitors the performance. The information collected by the RM is used to optimize the execution. In this paper, we propose and present the SW implementation of the RM for the MicroBlaze soft-core processor running the Linux OS and accelerated by the heterogeneous array of hardware accelerators.

In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realized? Here, we describe the European logarithmic microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful, and that for 32-bit work, logarithmic arithmetic may now be the technique of choice.

A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number system implementation of the RLS lattice IP core was used. Additionally, the extension by the order probability evaluation was implemented. Then, the core was wrapped in the System Generator. Finally, the generated EDK PCORE was modified to independent clock operation. Implemented solution makes possible evaluation of the RLS lattice filter of order 256 at 8 kHz input data rate in the best case. At the same time the order probability can be maintained. The implementation outperforms software solution up to 74 times and it is also performing 40% faster than other known solutions.

Although runtime dynamic reconfiguration of the FPGA devices has been an issue of the last decade, it has yet to achieve general recognition by the design community. The reasons for this are clear; there exists no straightforward design methodology, and the partitioning and CAD tool support is poor. This paper presents general concepts implemented in a placement and routing tool that provides an environment where designs that are partially and dynamically reconfigurable can be processed in order to be implemented on FPGAs that support this technology, such as the Atmel AT40K and AT94K series. The function of the tool is demonstrated on a simple real-world example.

Although runtime partial dynamic reconfiguration of FPGAs has been researched for many years and there have been a few FPGAs equipped with the required architectural features, it has yet to achieve general recognition by the commercial design community. This is mainly due to the lack of a professional CAD tool support. This paper presents extended concepts from E. L. Horta et al. (2002), Xilinx Application Note 290 (2004) and I. Robertson et al. (2002) implemented in a placement and routing tool. The tool supports creation of partially dynamically reconfigurable designs from input EDIF files and user-specified reconfiguration schedule down to bitstream generation for FPGAs that support this technology, such as the Atmel AT40K and AT94K series.

Presented high-level synthesis describes scheduling for wide class of DSP algorithms. Several FPGA vendors or even ASIC designs are targeted via Handel-C compiled by Celoxica DK3.1 compiler. Using the authors' approach, the designer can easily change type of used pipelined arithmetic modules and then check new performance. The optimal time schedule is found by cyclic scheduling using integer linear programming while minimizing the schedule period in the terms of clock cycles. Experimental results in HW implementation, performed on logarithmic arithmetic and floating-point arithmetic, confirm significant influence of the period on the resulting performance of DSP algorithms.

This paper presents a scheduling technique for a library of arithmetic logarithmic modules for FPGA illustrated on a RLS filter for active noise cancellation. The problem under assumption is to find an optimal periodic cyclic schedule satisfying the timing constraints. The approach is based on a transformation to monoprocessor cyclic scheduling with precedence delays. We prove that this problem is NP-hard and we suggest a solution based on integer linear programming that allows to minimize completion time. Finally experimental results of optimized RLS filter are shown.

Our poster introduces an innovative RLS Lattice filter implementation for FPGAs. The signal processing applications typically require wide numeric range, and that poses a problem when using an FPGA implementation. Our approach is based on arithmetic using logarithmic numeric representation (LNS). The test application - an adaptive noise canceller - has been optimized for the Xilinx Virtex devices. It consumes roughly 70% of all logic resources of the XCV800 device and all block memory cells. The filter orders up to 252 at 7 kHz sampling frequency have been achieved using the 19-bit LNS arithmetic. The maximum performance of the application is about 70 MFLOPs including i/o conversions. It has been shown that the custom filter design can be 10 times faster than commonly used solutions. This work was supported by the Ministry of Education of the Czech Republic under Project No. LN00B06.