Set reconciliation between different hosts to hold the same dataset is an important prerequisite in numerous distributed applications. Sending the entire dataset to achieve set reconciliation is inefficient if the majority of the data owned by each host is the same. Each host is required to send exclusive elements uniquely included in its set to the other to minimize communication complexity. This paper proposes an efficient algorithm for a host to identify its exclusive elements using the recursive comparison of ternary Bloom filters, each representing the signature of a subset of elements and used for filtering out subsets with identical elements. Hence, subsets with exclusive elements are identified, and elements included in the identified subsets are programmed to an invertible Bloom filter (IBF) to be sent to the other host. Thus, the number of elements programmed in the IBF is significantly reduced. Simulation results show that the proposed algorithm provides excellent performance compared with existing set reconciliation algorithms under the constraint of the same amount of data communication.

As a challenging attempt to replace a traditional data structure with a learned model, this paper proposes a learned functional Bloom filter (L-FBF) for a key--value storage. The learned model in the proposed L-FBF learns the characteristics and the distribution of given data and classifies each input. It is shown through theoretical analysis that the L-FBF provides a lower search failure rate than a single FBF in the same memory size, while providing the same semantic guarantees. For model training, character-level neural networks are used with pretrained embeddings. In experiments, four types of different character-level neural networks are trained: a single gated recurrent unit (GRU), two GRUs, a single long short-term memory (LSTM), and a single one-dimensional convolutional neural network (1D CNN). Experimental results prove the validity of theoretical results, and show that the L-FBF reduces the search failures by 82.8% to 83.9% when compared with a single FBF under the same amount of memory used.

As a simple probabilistic data structure, a Bloom filter consumes a small amount of memory in efficiently dealing with a large set of data elements. Bloom filters stored in on-chip memories have been popularly used as pre-filters to minimize unnecessary off-chip memory accesses. This paper proposes an interesting variant of a Bloom filter, the dual-load Bloom filter (DLBF) and shows that the proposed DLBF can be effective for implementing a name lookup algorithm. While Bloom filters usually hold a single type of information, which is either the membership in a given set or the return values of elements, the proposed DLBF holds both the membership and the return values in a single Bloom filter. As one of the trie-based name lookup algorithms developed for named data networking, a path-compressed trie compresses each path in a name prefix trie by removing empty nodes with a single child. This type of trie should be designed to hold skip values to represent the numbers of removed nodes in addition to the name prefixes stored in each node. This paper shows that the proposed DLBF can hold the skip values and the name prefixes to implement a path-compressed trie in an on-chip memory. Simulation results show that the proposed name lookup structure improves search performance by 33% using a much smaller amount of memory than previous Bloom filter-based structures.

Bloom filters have been employed in various fields because of its simple and effective structure in identifying the membership of an input. Since a Bloom filter can produce false positives, the positive results of a Bloom filter should be identified whether the positives are true or not by accessing the original database. A complement Bloom filter (C-BF) was introduced to identify the true positiveness of a given Bloom filter without accessing the original database. A critical problem of the C-BF is that every element included in the complement set of the given set should be programmed into the C-BF. Since the number of elements included in the complement set can be considerably large, the C-BF would require the significant amount of memory. In this paper, we claim that the elements that produce negative results from the given Bloom filter are not necessarily programmed into the C-BF, since Bloom filters never produce false negatives. In other words, we propose the Petit-BF (P-BF) which programs only the elements that cause false positives from the given Bloom filter. Simulation results and theoretical analysis show that the proposed method can achieve the same performance using a considerably smaller amount of memory.

In Named Data Networking (NDN), routers have caches to store frequently requested contents, and hence cache management scheme becomes a key factor for efficient content delivery. In this paper, we propose the sharing of cache summaries using a Bloom filter among neighboring routers for efficient content delivery and high cache utilization at NDN. When an Interest packet is received, a router can forward the Interest to a neighboring router which has the high potential of the requested content. The proposed scheme is evaluated by using ndnSIM, which is a NS-3 based named data networking simulator. Simulation results show that the summary sharing using our proposed method is beneficial in content diversity and average content delivery time.

IP address lookup operation determines the longest prefix matching each incoming destination address. As a fundamental operation for packet forwarding at Internet routers, search speed for routing table lookup is the most important performance metric. Previous researches have shown that the search performance of trie-based algorithms can be improved by adding on-chip Bloom filters. In these algorithms, an on-chip Bloom filter identifies the membership of a node in an off-chip trie, and the number of trie accesses is reduced, because the Bloom filter can filter out accesses to non-existing nodes in the trie. In this paper, we propose a new method of utilizing a Bloom filter for the IP address lookup problem. In the previous Bloom filter-based approach, false positiveness has to be identified by accessing the off-chip trie for every positive result, since false positives can produce wrong results. In our proposed approach, the false positiveness of a Bloom filter is not necessarily identified by making false positives not mislead the search. Hence the number of off-chip trie accesses are significantly reduced. Simulation results show that the best matching prefix can be found with a single off-chip access in average and in the worst-case with the reasonable size of a Bloom filter in our proposed method.

Packet classification is one of the most essential functions that Internet routers should perform at wire-speed for every incoming packet. An area-based quad-trie (AQT) for packet classification has an issue in search performance since many rule nodes can be encountered in a search procedure. A leaf-pushing AQT improves the search performance of the AQT by making a single rule node exist in each search path. This paper proposes a new algorithm to improve the search performance of the leaf-pushing AQT further. The proposed algorithm builds a leaf-pushing AQT using a Bloom filter and a hash table stored in on-chip memories. The level of a rule node and a pointer to a rule database are identified by sequentially querying the Bloom filter and by accessing the hash table, respectively.

For the successful realization of content-centric network, it is essential to design an efficient forwarding engine that performs high-speed name lookup. This paper proposes the use of a hashing-based name prefix trie and a Bloom filter. In the proposed approach, an off-chip hash table storing the trie is accessed when the Bloom filter states that the node exists in the trie. In accessing the hash table depending on the result of a Bloom filter, we propose two algorithms that have different search strategies. The first algorithm accesses the hash table for every positive result in a Bloom filter, while the second algorithm firstly attempts to determine the longest matching length using Bloom filter queries. The simulation result shows that the proposed approach can provide the output face of each input name, with a single hash table access on average and with two hash table accesses in the worst-case.

Many IP address lookup approaches employ Bloom filters to obtain a high-speed search performance. Especially, the search performance of trie-based algorithms can be significantly improved by adding Bloom filters, because Bloom filters can determine whether a node exists in a trie without accessing the trie. The false positive rate of a Bloom filter must be reduced to enhance the lookup performance. One important characteristic of a trie is that all the ancestors of a node are also stored. The proposed IP lookup algorithm utilizes this characteristic in reducing the false positive rate of a Bloom filter without increasing the Bloom filter size. When a Bloom filter produces a positive result for a node of a trie, we propose to check whether the ancestors of the node are also positives. Because Bloom filters have no false negatives, the negative of the ancestor means that the positive of the node is false. Simulation results show that the false positive rate is reduced up to 67\% using the exact same amount of memory. The proposed approach can be applied to other trie-based algorithms employing Bloom filters.

As one of efficient IP address lookup approaches, binary search on trie levels (BSL) provides high-speed search performance. It has been recently studied that the search performance of BSL algorithms can be further improved by adding a Bloom filter. The Bloom filter has a role identifying whether there is a node beforehand so that unnecessary trie accesses can be avoided. Leaf-pushing BSL (LBSL) algorithm performs the binary search on trie levels in a leaf-pushing trie. Since every prefix is located in leaves in this trie, it has an advantage that the search can be immediately finished when a prefix is encountered. However, because of prefix replication caused in the leaf-pushing process, the trie becomes dense, and hence adding a Bloom filter does not give much impact in improving the search performance. The motivation of this paper is to keep the sparseness of a trie to get search performance improvement by a Bloom filter in performing the binary search on trie levels in a leaf-pushing trie. The proposed algorithm defines control levels, and an internal prefix is pushed up to the closest control level. By limiting the levels of leaf-pushing, the prefix replication is significantly reduced, and hence a Bloom filter can provide an increased efficiency. Simulations using 5 actual routing sets with different sizes show that the search performance improvement by a Bloom filter is more significant than in the previous LBSL approach, and the average number of trie accesses is 2 to 3 in performing an IP address lookup in our proposed algorithm.

High-speed IP address lookup is essential to achieve wire-speed packet forwarding in Internet routers. Ternary content addressable memory (TCAM) technology has been adopted to solve the IP address lookup problem because of its ability to perform fast parallel matching. However, the applicability of TCAMs presents difficulties due to cost and power dissipation issues. Various algorithms and hardware architectures have been proposed to perform the IP address lookup using ordinary memories such as SRAMs or DRAMs without using TCAMs. Among the algorithms, we focus on two efficient algorithms providing high-speed IP address lookup: parallel multiple-hashing (PMH) algorithm and binary search on level algorithm. This paper shows how effectively an on-chip Bloom filter can improve those algorithms. A performance evaluation using actual backbone routing data with 15,000-220,000 prefixes shows that by adding a Bloom filter, the complicated hardware for parallel access is removed without search performance penalty in parallel-multiple hashing algorithm. Search speed has been improved by 30-40 percent by adding a Bloom filter in binary search on level algorithm.

Decision-tree-based packet classification algorithms such as HiCuts, HyperCuts, and EffiCuts show excellent search performance by exploiting the geometrical representation of rules in a classifier and searching for a geometric subspace to which each input packet belongs. However, decision tree algorithms involve complicated heuristics for determining the field and number of cuts. Moreover, fixed interval-based cutting not relating to the actual space that each rule covers is ineffective and results in a huge storage requirement. A new efficient packet classification algorithm using boundary cutting is proposed in this paper. The proposed algorithm finds out the space that each rule covers and performs the cutting according to the space boundary. Hence, the cutting in the proposed algorithm is deterministic rather than involving the complicated heuristics, and it is more effective in providing improved search performance and more efficient in memory requirement. For rule sets with 1000-100 000 rules, simulation results show that the proposed boundary cutting algorithm provides a packet classification through 10-23 on-chip memory accesses and 1-4 off-chip memory accesses in average.

High-speed IP address lookup is essential to achieve wire speed packet forwarding in Internet routers. The longest prefix matching for IP address lookup is more complex than exact matching because it involves dual dimensions: length and value. This paper presents a new formulation for IP address lookup problem using range representation of prefixes and proposes an efficient binary trie structure named a priority trie. In this range representation, prefixes are represented as ranges on a number line between 0 and 1 without expanding to the maximum length. The best match to a given input address is the smallest range that includes the input. The priority trie is based on the trie structure, with empty internal nodes in the trie replaced by the priority prefix which is the longest among those in the subtrie rooted by the empty nodes. The search ends when an input matches a priority prefix, which significantly improves the search performance. Performance evaluation using real routing data shows that the proposed priority trie is very good in performance metrics such as lookup speed, memory size, update performance, and scalability.

This paper proposes a new IP address lookup using a Bloom filter. The proposed algorithm is based on binary search on trie levels, and a Bloom filter pre-filters the levels which do not have matching nodes in performing the binary search on levels. Hence the number of memory access which affects the search performance is greatly reduced. Simulation result shows that an IPv6 address lookup can be performed with 1--3 memory accesses in average for an IPv6 routing data set with 1096 prefixes.

We propose an efficient binary search algorithm for IP address lookup in the Internet routers. While most of the previous binary search algorithms do not provide a balanced search, the proposed algorithm provides a perfectly balanced search, and hence it provides excellent search performance and scalability toward large routing tables.

Packet classification is one of the major challenges for next generation routers since it involves complicated multi-dimensional search as well as it should be performed in wire-speed for all incoming packets. Area-based quad-trie is an excellent algorithm in the sense that it constructs a two-dimensional trie using source and destination prefix fields for packet classification. However, it does not achieve good search performance since search is linearly performed for prefix length. In this paper, we propose a new packet classification algorithm which applies binary search on prefix length to the area-based quad-trie. In order to avoid the pre-computation required in the binary search on length, the proposed algorithm constructs multiple disjoint tries depending on relative levels in rule hierarchy. We also propose two new optimization techniques considering rule priorities. For different types of rule sets having about 5000 rules, performance evaluation result shows that the average number of memory accesses is 18 to 67 and the memory consumption is 22 to 41 bytes per rule.

Error concealment (EC) has been adopted to reconstruct lost information for video transmission over wireless networks. For intra-frame EC in H.264 video, only spatial correlations between neighboring macroblocks have been applied for spatial interpolation of the lost macroblock. In this paper, we first propose a simple temporal EC,which uses the temporal correlations between neighboring frames and improves the EC performance for intra-frame in H.264. Then we propose a new hybrid EC method for intra-frame in H.264, which combines the spatial EC and the temporal EC adaptively. Simulation results show that the proposed temporal EC shows substantial PSNR improvement compared to the previous spatial EC in H.264 intra-frame when the amount of motion is small. The proposed hybrid EC achieves further PSNR improvement compared to the temporal ECwhen the amount of motion is rather large.

Fast IP address lookup in the Internet routers is essential to achieve packet forwarding in wire-speed. The longest prefix matching for the IP address lookup is more complex than exact matching because of its dual dimensions, length and value. By thoroughly studying the current proposals for the IP address lookup problem, we find out that binary search could be a low-cost solution while providing high performance. Most of the existing binary search algorithms based on trie have simple data structures which can be easily implemented, but they have empty internal nodes. Binary search algorithms based on prefix values do not have empty nodes, but they either construct unbalanced trees or create extra nodes. In this paper, a new IP address lookup algorithm using a priority trie is proposed. The proposed algorithm is based on the trie structure, but empty internal nodes are replaced by priority prefixes. The longest prefix matching in the proposed algorithm is more efficiently performed since search can be immediately finished when input is matched to a priority prefix. The performance evaluation results show that the proposed priority trie has very good performance in terms of the memory requirement, the lookup speed, and the scalability.

The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used tools in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.

This paper presents a fixed-point error analysis for the unified systolic array implementation of 2-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse discrete cosine transform (IDCT). Closed form expressions for the mean and variance of fixed-point rounding-errors and truncation-errors are derived. Simulation results are provided to verify the analysis. Simulations designed to find the minimum word-length which satisfies IEEE requirements for the implementation of an 8/spl times/8 IDCT are also performed. Simulation results show that the proposed systolic array is more robust for the fixed-point error than other existing implementations for DCT/IDCT.

One of the most challenging problems for VLSI implementation of the discrete Fourier transform (DFT) is to efficiently implement multidimensional discrete Fourier transforms with systolic architectures. This paper presents a multidimensional systolic array for performing the multidimensional DFT. Extensions of the multidimensional systolic array are widely searched for the prime-factor computation or the 2/sup n/-point decomposed computation of one-dimensional (1-D) DFT. The essence of the proposed multidimensional systolic array is to combine different types of semi-systolic arrays into one array so that the resulting array becomes truly systolic. This systolic array does not require any preloading of input data and it produces output data at boundary PEs. No networks for intermediate spectrum transposition between constituent 1-dimensional transforms are required; therefore the entire processing is fully pipelined.

A new design of a systolic array for computing the discrete cosine transform (DCT) based on prime-factor decomposition is presented. The basic principle of the proposed systolic array is that one-dimensional (1-D) DCT can be decomposed to a 2-dimensional (2-D) DCT by input and output index mappings and the 2-D DCT is computed efficiently on a 2-D systolic array. We modify Lee's input index mapping method in order to construct one input mapping table instead of three input index mapping tables. The proposed systolic array avoids the need for the array transposer that was required by earlier implementations for the prime-factor DCT algorithms, and thus all processing can be pipelined. The proposed design of systolic array provides a simple and regular structure, which is well suited for VLSI implementation.

A new approach for computing the 2-D DFT (discrete Fourier transform) and 2-D DCT (discrete cosine transform) is presented. A new design of a systolic array for transposed matrix multiplication is also shown in this paper. The new 2-D DFT/DCT avoids the need for the array transposer that was required by earlier implementations, and all processing can be pipelined easily. This approach employs a simple and regular structure that is well suited for VLSI implementation. This array can be easily scaled without modifying the basic control scheme and PE structure.>