The IEEE Std. 1687 facilitates flexible access to on-chip instruments through the JTAG test-access port. This flexibility enables the minimization of the overall access time (OAT), and a number of techniques have been proposed in the literature to achieve this goal. However, the OAT is still high for instruments that require a large amount of test data if this data is shifted through the scan chain serially. In order to further reduce the OAT, we present an efficient test-scheduling method that exploits broadcast and hardware parallelism for instrument access. A broadcast scheduling method is synergistically combined with three parallel IJTAG designs. We show that under different cost criteria, we can select the most efficient parallel IJTAG design such that the equivalent access time (EAT) is minimized. In addition, an interconnect fabric design and an integer-linear-programming method is used to balance the lengths of multiple scan chains. Two industry chip designs and three IJTAG benchmarks are used to evaluate the effectiveness of the proposed method.

Modern large system-on-chip (SoC) designs typically have hundreds of cores. Each core requires a certain number of input/output test channels. At the chip level, however, the total number of test pins is limited such that all core-level test channels cannot be accessed at the same time. Therefore, hierarchical pattern retargeting is required for SoC test. Test scheduling algorithms can be applied to reduce the total test time. In this paper, we add the EDT architectures as one additional dimension of parameter into the prior test scheduling algorithm. Experimental results based on real case studies show that with the proposed flow, the test time can be further reduced up to approximately 24%.

The IEEE Std. 1687 facilitates flexible access to on-chip instruments through the JTAG test-access port. This flexibility enables the minimization of the overall access time (OAT), and a number of techniques have been proposed in the literature to achieve this goal. However, the OAT is still high for instruments that require a large amount of test data if this data is shifted through the scan chain serially. In order to further reduce the OAT, we present an efficient test-scheduling method that exploits broadcast and hardware parallelism for instrument access. A broadcast scheduling method is synergistically combined with three parallel IJTAG designs. We show that under different cost criteria, we can select the most efficient parallel IJTAG design such that the equivalent access time (EAT) is minimized. Two industry chip designs and three IJTAG benchmarks are used to evaluate the effectiveness of the proposed method.

The IEEE Std. 1687 enables flexible access to on-chip instruments through the JTAG test-access port. This flexibility enables the minimization of the overall access time (OAT), and a number of techniques have been proposed to achieve this goal. However, these techniques do not utilize the broadcast feature in the 1687 network. In order to further reduce the OAT, we present an efficient test-scheduling method that exploits the broadcast feature for instrument access. Two optimization solutions are then proposed - the first solution minimizes the OAT without the retargeting time, while the second one reorders the configurations so as to minimize the overall retargeting time among configurations. Three industry test cases are used to evaluate the effectiveness of the proposed method.

This paper presents approaches to reduce scan test data volume for SoC designs in EDT environment. They target different factors impacting scan test data volume - scan channel count, pattern count and shift cycles. In the experiments on an industrial SoC design, up to 23% scan test data volume can be reduced.

This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at-speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device's defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These features include equivalent clock merging for routing considerations, programmable shift modes for overheat considerations, configurable capture modes for yield loss and IR-drop considerations, as well as BIST signature diagnosis, masked-chain diagnosis, and one-chain diagnosis at the system level. Experimental results have successfully demonstrated the feasibility of using the proposed features for system-level test and diagnosis.