Recently a prior work has been proposed to improve the power distribution network (PDN) design with some practical methodologies. However, we found that such approach will cause redundant resources, resulting in the waste of the metal application. In this paper, we present a more effective design flow to automatically generate a PDN verified by the commercial tool without IR-Drop violation. We propose an analytical model and consider the different types of macros to determine the total metal width of PDN. Moreover, the optimization is based on a centroid learning method from unsupervised learning to consolidate PDN. Our work has experimented on real designs in 65 nm process, 0.18 um generic process, and 40 nm process. The results show that our framework can satisfy the given IR-Drop constraints and simultaneously save lots of metal resource (means no overdesign).

The emerging compressed sensing (CS) technique provides lightweight data compression with zero-cost encryption. Therefore, CS enables reduced-complexity designs for sensor nodes and saves transmission power in wireless sensor networks (WSNs). However, CS's linear encoding process makes it vulnerable to several attacks, which may lead to privacy leakage issues. In this article, leveraging the characteristic that CS reconstruction is sensitive to measurement noise, we propose a CS-based watermark cryptosystem for WSNs. In the front-end sensor, a low-dimension watermark is embedded in measurements. In the back-end solver, we present a CS-based watermark decryption/reconstruction engine for the Internet of Things (IoT) gateway. Without synchronization of the key, the proposed cryptosystem can resist ciphertext-only attack and known-plaintext attack effectively. Furthermore, leveraging watermarks as a digital signature, the proposed engine can detect denial of service attack effectively before signal reconstruction. For real-time signal processing, multiple-indices updating algorithm and VLSI architecture are applied to eliminate the throughput degradation from watermark removal. Finally, this CS decoder is fabricated in 40-nm CMOS, and it can support the simultaneous reconstruction of over 10 000 wireless sensors in real time while offering synchronization-free watermark decryption. Therefore, the proposed cryptosystem is suitable for the emerging IoT applications that need encryption strength with limited complexity.

The emerging compressed sensing (CS) technique enables new reduced-complexity designs of sensor nodes and helps to save overall transmission power in wireless sensor network. Because of the linearity of its encoding process, CS is vulnerable to Ciphertext-Only Attack (COA) and Known-Plaintext Attack (KPA). The prior works use multiple sensing matrices as the shared secret key, however, the complexity overhead of frontend sensor and synchronization issue arising from multiple keys should be well considered. In this paper, by leveraging the characteristic of CS that is sensitive to destroyed sparsity, a low-dimension watermark is randomly chosen and embedded in measurement in front-end part. Then, in back-end solver, the proposed decrypting basis can decipher the encrypted signals without synchronization. Simulation results show that the proposed scheme achieves effective protection against COA and KPA with only 5% storage overhead. It furtherly eases the encryption complexity of front-end sensor by 98.8% under our experiments.

Next-decade computing power and interconnect bottle-neck challenge conventional IC design due to the ever increasing demands for high frequency and great bandwidth. Three-dimensional large-scale integration (3D-LSI) provides an opportunity to realize such high performance cores while reducing long latency. In this paper, we present a reference flow for the implementation of 3D via-last ICs in scalable face-to-back bonding style which leverages a mature set of 2D IC physical design tools. The first enabling technology of 3D-LSI is through-silicon via (TSV). Two kinds of TSV diameters are exemplified in the flow, namely, 5¿m and 50¿m. We propose an easy-to-adopt method to address the TSV-aware mixed-sized placement by considering the obstructions generated from adjacent-tier's floorplan, subject to certain TSV alignment constraints. Furthermore, the technique of clock tree synthesis (CTS) for a homogeneous die stack is developed to dramatically reduce the clock latency and skew. The mixed-sized placement and CTS of each tier can be done without iteration. To the best of our knowledge, no work has ever been published in literature discussing CTS for 3D via-last integration in a face-to-back fashion. Finally, to complete the proposed flow 2D timing-driven routing and modified off-line design rule check (DRC) and layout versus schematic (LVS) verification are performed very well.