EDBT 2026 Demo / reviewers in the wild / expert
Chang-Ho Ryu
dblp:70/919
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 61% Processor architecture and microarchitecture · 30% Integrated circuit design · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware/software co-design
application-specific instruction set processor design |
0.0 | 1 | 1998 | MetaCore: An Application Specific DSP Development System · DAC 1998 |
Electronic design automation
high-level synthesis |
0.0 | 1 | 1998 | MetaCore: An Application Specific DSP Development System · DAC 1998 |
Processor architecture and microarchitecture › instruction set architecture
instruction set design |
0.0 | 1 | 1998 | MetaCore: An Application Specific DSP Development System · DAC 1998 |
Integrated circuit design › digital signal processing circuits
digital signal processor design |
0.0 | 1 | 1998 | MetaCore: An Application Specific DSP Development System · DAC 1998 |
Methods — techniques the papers use, named apart from their topics
design methodology · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | Metacore: A Configurable and Instruction Level Extensible DSP CoreabstractThe design of application-specific processor for DSP applications is not only driven by low-cost requirements, but also needs to fulfil constraints in terms of short development time. MetaCore, a configurable and instruction-level extensible DSP core, can effectively satisfy these requirements by providing a high degree of customization to the given application. In this paper, we present architectural concept of MetaCore and the MetaCore development platform. And we also present the first-generation MetaCore product version, MDSP16, which is a 16-by-16 fixed-point DSP processor. MDSP1.6 was implemented using 0.6 /spl mu/m TLM CMOS technology and has 50 MIPS peak performance. Jin-Hyuk Yang, Byung-Woon Kim, Sang-Jun Nam, Chang-Ho Ryu, Jang-Ho Cho, Chong-Min Kyung |
ASP-DAC | 5 |
| 1998 | MetaCore: An Application Specific DSP Development SystemabstractThis paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
DAC | 6 |