Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Tadeusz Tomczak

dblp:70/922 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2018
0000-0002-7206-4199ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 50% Parallel and multicore computing · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
GPU computing
0.312018
Sparse Geometries Handling in Lattice Boltzmann Method Implementation for Graphic Processors · IEEE Trans. Parallel Distributed Syst. 2018
Parallel and multicore computing › parallel computing
parallel scientific computing
0.312018
Sparse Geometries Handling in Lattice Boltzmann Method Implementation for Graphic Processors · IEEE Trans. Parallel Distributed Syst. 2018

Methods — techniques the papers use, named apart from their topics

tiling · 0.3lattice boltzmann method · 0.3
YearPublicationVenuePosition
2018 Sparse Geometries Handling in Lattice Boltzmann Method Implementation for Graphic Processors
abstract
We describe a high-performance implementation of the lattice Boltzmann method (LBM) for sparse geometries on graphic processors. In our implementation we cover the whole geometry with a uniform mesh of small tiles and carry out calculations for each tile independently with proper data synchronization at the tile edges. For this method, we provide both a theoretical analysis of complexity and the results for real implementations involving two-dimensional (2D) and three-dimensional (3D) geometries. Based on the theoretical model, we show that tiles offer significantly smaller bandwidth overheads than solutions based on indirect addressing. For2D lattice arrangements, a reduction in memory usage is also possible, although at the cost of diminished performance. We achieved a performance of 682 MLUPS on GTX Titan (72 percent of peak theoretical memory bandwidth) for the D3Q19 lattice arrangement and double-precision data.
Tadeusz Tomczak, Roman G. Szafran
IEEE Trans. Parallel Distributed Syst.1