The problem of flipping modules about their horizontal and/or vertical axes so as to minimize the estimated total wire length is considered. Polynomial time algorithms are proposed for some classes of module layouts. Further, it is shown that a simple greedy heuristic often outperforms the neural network and simulated annealing heuristics proposed earlier for this problem.>

The problem of selecting a realization for each of the blocks in a VLSI chip's floorplan so that the area of the floorplan is minimized is considered. This is done by repeatedly replacing primitive superblocks by equivalent basic blocks. A linear time algorithm to determine all the needed primitive superblocks is developed. Equivalent basic blocks are found by using L. Stockmeyer's (1983) algorithm if the primitive superblock has a slicing structure and by using branch-and-bound if not. Experimental results are provided.>

It is shown that obtaining the optimal orientations of modules to minimize the length of the longest wire is NP-hard. If each module is permitted only two possible orientations, this can be done in linear time. When all four orientations are permissible and wires are restricted to connect modules whose separation is bounded by some constant, then the problem can also be solved in linear time.>