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Tomoyoshi Funazaki

dblp:70/9350 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
asynchronous circuit design
0.212014
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router · IEEE Trans. Computers 2014
Integrated circuit design › asynchronous circuit design
delay-insensitive codes
0.212014
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router · IEEE Trans. Computers 2014
Integrated circuit design
digital circuit design
0.212014
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router · IEEE Trans. Computers 2014

Methods — techniques the papers use, named apart from their topics

level-encoded dual-rail encoding · 0.2
YearPublicationVenuePosition
2014 High-Throughput Compact Delay-Insensitive Asynchronous NoC Router
abstract
A new asynchronous delay-insensitive data-transmission method based on level-encoded dual-rail (LEDR) encoding with novel packet-structure restriction is proposed to realize a high-throughput network-on-chip (NoC) router together with a compact hardware. The use of LEDR encoding makes communication steps and the registers being used half in comparison with four-phase dual-rail encoding because the spacer information of the four-phase one is eliminated, which significantly improves the network throughput. By using the proposed packet structure, the phase information of header and tail flits is uniquely determined. Since the router can be asynchronously controlled by ignoring the phase information, the circuit is compactly implemented. As a result, the proposed asynchronous NoC router on a 0.13-μm CMOS technology, has a 90 percent increase in throughput and a 34 percent decrease in energy dissipation with 25 percent area overhead in comparison with a conventional four-phase asynchronous NoC router under a postlayout simulation. Under a random traffic pattern in a 4 x 4 2D mesh topology, the proposed asynchronous NoC has a 140 percent increase in throughput and half packet latency compared with the conventional one. We also fabricate the asynchronous NoC based on the proposed router on a 0.13-μm CMOS technology and demonstrate the chip correctly operates under a supply voltage of 0.6 to 1.8 V.
Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu
IEEE Trans. Computers3