Demo Data from EDBT 2026 / reviewers in the wild / expert
Hsien-Kai Hsin
dblp:70/9353
· DBLP profile ↗
6ranked-venue papers
3as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
6 papers |
Interconnection networks and networks-on-chip · 78% Electronic design automation · 14% Hardware reliability and fault tolerance · 6% |
Topics — the 12 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › routing algorithms
adaptive routing |
0.8 | 4 | 2015 | Ant Colony Optimization-Based Adaptive Network-on-Chip Routing Framework Using Network Information Region · IEEE Trans. Computers 2015 Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems · IEEE Trans. Computers 2015 Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2014 |
Interconnection networks and networks-on-chip › routing algorithms
fault-tolerant routing |
0.5 | 2 | 2017 | Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2017 Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Interconnection networks and networks-on-chip
routing algorithms |
0.3 | 1 | 2017 | Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2017 |
Interconnection networks and networks-on-chip
router architecture |
0.3 | 2 | 2015 | Ant Colony Optimization-Based Adaptive Network-on-Chip Routing Framework Using Network Information Region · IEEE Trans. Computers 2015 Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Electronic design automation › physical design
routing |
0.2 | 1 | 2015 | Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems · IEEE Trans. Computers 2015 |
Interconnection networks and networks-on-chip › traffic management
traffic balancing |
0.2 | 1 | 2015 | Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems · IEEE Trans. Computers 2015 |
Interconnection networks and networks-on-chip › routing algorithms
congestion-aware routing |
0.2 | 1 | 2014 | Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2014 |
Electronic design automation › physical design › routing › message routing
network-on-chip routing |
0.2 | 1 | 2014 | Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2014 |
Hardware reliability and fault tolerance
manufacturing defects |
0.1 | 1 | 2017 | Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2017 |
Hardware reliability and fault tolerance › soft errors
transient fault |
0.1 | 1 | 2017 | Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2017 |
Processor architecture and microarchitecture
chip multiprocessor |
0.1 | 1 | 2014 | Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip Systems · IEEE Trans. Parallel Distributed Syst. 2014 |
Interconnection networks and networks-on-chip
congestion control |
0.1 | 1 | 2014 | Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Methods — techniques the papers use, named apart from their topics
ant colony optimization · 0.8saturation throughput evaluation · 0.3buffer occupancy analysis · 0.3cascaded routing · 0.2exponential moving average · 0.2contention prediction · 0.2buffer level rate-of-change · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip SystemsabstractNetwork-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing (PDA-FTR) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead. Yu-Yin Chen, En-Jui Chang, Hsien-Kai Hsin, Kun-Chih Chen, An-Yeu Wu |
IEEE Trans. Parallel Distributed Syst. | 3 |
| 2015 | Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip SystemsabstractThe regular topology of mesh-based network-on-chip (NoC) provides flexible and scalable architecture for chip multiprocessor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. In the field of wide area networks (WANs), ant colony optimization (ACO) has been applied to an adaptive routing for improving performance and achieving load balancing. Nevertheless, if we directly apply ACO to NoC systems, the implementation cost of ACO is excessively high. To overcome this problem, the ACO-based adaptive routing must be reformulated while considering both router cost and NoC efficiency. This work proposes the regional ACO-based cascaded adaptive routing (RACO-CAR) scheme with the following techniques: 1) table elimination by removing redundant information, 2) table sharing by grouping pheromone information to merge table content, and 3) cascaded routing that assigns traffic to different uncongested regions to balance traffic. Our experimental results demonstrate that the RACO-CAR scheme has an improvement of 3.9-36.84 percent in saturation throughput compared with existing adaptive routing schemes. The implementation cost of the RACO-CAR router is only 37.4 percent of that of the ACO-based router with full routing table. Therefore, the proposed RACO-CAR scheme has high area efficiency, defined as saturation throughput divided by the total cost of router. En-Jui Chang, Hsien-Kai Hsin, Chih-Hao Chao, Shu-Yen Lin, An-Yeu Wu |
IEEE Trans. Computers | 2 |
| 2015 | Ant Colony Optimization-Based Adaptive Network-on-Chip Routing Framework Using Network Information RegionabstractThe network-on-chip (NoC) system can provide more scalable and flexible on-chip interconnection compared with system bus. The performance of on-chip adaptive routing algorithms greatly relies on the adopted network information. To the best our knowledge, previous routing algorithms utilize either spatial or temporal network information to improve performance. However, few works have established a framework on analyzing the network information nor showed how to integrate the spatial and temporal network information. In this paper, we define the network information region (NIR) framework for NoC systems. The NIR can indicate arbitrary combinations of network information and corresponding routing algorithms. We demonstrate how to apply NIR on analyzing the adaptive routing algorithms. To further demonstrate how NIR can help to integrate the spatial or temporal network information, we propose the ACO-based pheromone diffusion (ACO-PhD) adaptive routing framework based on the NIR. By diffusing the pheromone outward, spatial and temporal network information can be exchanged among adjacent routers. The range (i.e., size and shape) of the NIR is controllable by setting the parameters in the ACO-PhD algorithm. We show that we can reconfigure the ACO-PhD algorithm to each routing algorithm in its NIR subsets by adjusting the parameter settings. Finally, we implement and analyze the hardware design of corresponding router architecture. The results show an improvement of 4.86-16.93 percent on network performance and the highest area efficiency is achieved by the proposed algorithm. Hsien-Kai Hsin, En-Jui Chang, Kuan-Yu Su, An-Yeu Wu |
IEEE Trans. Computers | 1 |
| 2014 | Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip SystemsabstractNetwork-on-chip systems can achieve higher performance than bus systems for chip multiprocessor systems. However, as the complexity of the network increases, the channel and switch congestion problems become major performance bottlenecks. An effective adaptive routing algorithm can help minimize path congestion through load balancing. However, conventional adaptive routing schemes only use channel-based information to detect the congestion status. Due to the lack of switch-based information, channel-based information is difficult to reveal the real congestion status along the routing path. Therefore, in this paper, we remodel the path congestion information to show hidden spatial congestion information and improve the effectiveness of routing path selection. We propose a path-congestion-aware adaptive routing (PCAR) scheme based on the following techniques: 1) a path-congestion-aware selection strategy that simultaneously considers switch congestion and channel congestion, and 2) a contention prediction technique that uses the rate of change in the buffer level to predict possible switch contention. The experimental results show that the proposed PCAR scheme can achieve a high saturation throughput with an improvement of 15.4%-48.7% compared to existing routing schemes. The proposed PCAR method also includes a VLSI architecture, which has higher area efficiency with an improvement of 16%-35.7% compared with the other router designs. En-Jui Chang, Hsien-Kai Hsin, Shu-Yen Lin, An-Yeu Wu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2014 | Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip SystemsabstractThe advanced deep submicrometer technology increases the risk of failure for on-chip components. In advanced network-on-chip (NoC) systems, the failure constrains the on-chip bandwidth and network throughput. Fault-tolerant routing algorithms aim to alleviate the impact on performance. However, few works have integrated the congestion-, deadlock-, and fault-awareness information in channel evaluation function to avoid the hotspot around the faulty router. To solve this problem, we propose the ant colony optimization-based fault-aware routing (ACO-FAR) algorithm for load balancing in faulty networks. The behavior of an ant colony while facing an obstacle (failure in NoC) can be described in three steps: 1) encounter; 2) search; and 3) select. We implement the corresponding mechanisms as: 1) notification of fault information; 2) path searching mechanism; and 3) path selecting mechanism. With proposed ACO-FAR, the router can evaluate the available paths and detour packets through a less-congested fault-free path. The simulation results show that this paper has higher throughput than related works by 29.1%–66.5%. In addition, ACO-FAR can reduce the undelivered packet ratio to 0.5%–0.02% and balance the distribution of traffic flow in the faulty network. Hsien-Kai Hsin, En-Jui Chang, Chia-An Lin, An-Yeu Wu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2014 | Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip SystemsabstractNetworks-on-Chip (NoC) provides a regular and scalable design architecture for chip multi-processor (CMP) systems. The Ant Colony Optimization (ACO) is a distributed algorithm. Applying ACO to selection models of adaptive routing can improve NoC performance. Currently, ACO-based selection only uses the historical traffic information. While additional temporal and spatial information provides better approximation of network status for global load-balancing. In this paper, we first consider the temporal enhancement of congestion information. We propose the Multi-Pheromone ACO-based (MP-ACO) selection scheme which adopts the concept of Exponential Moving Average (EMA) from stock market. We implement a novel ACO system where ants lay two kinds of pheromones with different evaporation rates. The temporal pheromone variation can help to capture hidden-state dependencies of upcoming congestion status. Secondly, to acquire the spatial range of congestion information, we propose Regional-Aware ACO-based (RA-ACO) selection to record historical buffer information from routers within two-hop of distances, which helps to extend spatial pheromone coverage. Information provided by the proposed two schemes improves the system performance. Simulation results show that MP-ACO and RA-ACO with Odd-Even routing algorithm yields an improvement in saturation throughput over OBL and NoP selection by 14.38 percent and 18.64 percent, respectively. The router architectures for the proposed schemes are also implemented and analyze with small hardware overhead. Hsien-Kai Hsin, En-Jui Chang, An-Yeu Wu |
IEEE Trans. Parallel Distributed Syst. | 1 |