Low-power wireless sensor networks have demonstrated their potential for the detection of rare events such as rockfalls and wildfires, where rapid reporting as well as long-term energy-efficient operation is vital. However, current systems require periodic synchronization to maintain network coordination, heavily rely on node placement or use costly long-range links to infrastructure. We present STeC, a novel wireless communication design that directly exploits the spatial and temporal correlation of signals from the sensed phenomenon to orchestrate event-based communication. We leverage the locality of a co-detection, where a physical event triggers multiple sensors quasi-simultaneously, to efficiently collect, characterize and report sensor data. This eliminates the overhead of periodic network activity and centralized control, resulting in more energy-efficient communication with a lower, more consistent detection latency. In doing so, we propose a fundamentally new approach to avoid the elementary conflict between duty cycle and latency requirements immanent to synchronous protocols by exploiting correlated sensor signals for networking. Experiments using real-world traces of a natural hazard detection application show that STeC reduces the detection latency by up to 87 % compared to standard single-hop communication and outperforms traditional schedule-based methods by up to 58.4 x in energy efficiency.

In natural hazard warning systems fast decision making is vital to avoid catastrophes. Decision making at the edge of a wireless sensor network promises fast response times but is limited by the availability of energy, data transfer speed, processing and memory constraints. In this work we present a realization of a wireless sensor network for hazard monitoring based on an array of event-triggered single-channel micro-seismic sensors with advanced signal processing and characterization capabilities based on a novel co-detection technique. On the one hand we leverage an ultra-low power, threshold-triggering circuit paired with on-demand digital signal acquisition capable of extracting relevant information exactly and efficiently at times when it matters most and consequentially not wasting precious resources when nothing can be observed. On the other hand we utilize machine-learning-based classification implemented on low-power, off-the-shelf microcontrollers to avoid false positive warnings and to actively identify humans in hazard zones. The sensors' response time and memory requirement is substantially improved by quantizing and pipelining the inference of a convolutional neural network. In this way, convolutional neural networks that would not run unmodified on a memory constrained device can be executed in real-time and at scale on low-power embedded devices. A field study with our system is running on the rockfall scarp of the Matterhorn Hörnligrat at 3500 m a.s.l. since 08/2018.

The Dual Processor Platform (DPP) is a novel architecture template for networked embedded systems based on a strictly asynchronous processor interconnect that allows to minimize interference with a proven predictable behavior [7]. Contrary to traditional platforms [1, 5] DPP tries to mitigate interference by isolating different tasks and mapping them onto dedicated hardware resources. Typically, two different task sets - (i) sensing/actuation/data processing and (ii) communication - are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements. Such hardware partitioning is a standard approach, frequently found in more complex sensor system implementations [2]. While the communication processor handles wireless packet transmission and reception, the application processor is dedicated to the sensor data acquisition, processing and actuation. But this strict separation of resources and function also requires a processor interconnect: BOLT [7], a stateful processor interconnect specifically designed based on this paradigm allows a strict decoupling of the power, clock and time domains of the two processing elements by allowing only asynchronous message passing between the two. The strict limitation to an asynchronous interface allows for predictable run-time behavior that, in addition to typical behavior observed from experiments, has been formally verified [7]. The most notable advantages of this approach are:

Designing and testing low-power wireless communication protocols often requires experimental deployments on real hardware in realistic settings. Infrastructure testbeds have the advantage that they allow reproducible results using different network configurations. However, most testbeds are either in- or outdoor only and do not span long and short ranges at the same time. In this work, we present an extension to the popular FlockLab testbed on a campus-scale in order to better support testing of long-range communciation, for example using the LoRa modulation. Different to existing LoRa test networks where specific protocol layers are fixed, we support custom modification above the physical hardware (above PHY) which allows the development and testing of alternative full custom MAC layers that are not based on LoRaWAN.

We present a heterogeneous system architecture for event-triggered wireless sensing capable of supporting high spatial resolution. The key differentiator between the proposed architecture and alternative state-of-the-art approaches is the ability to simultaneously maximize operational lifetime and minimize end-to-end latency of detected events. Our novel architecture takes advantage of heterogeneity with respect to the operation of the wireless communication protocol and the construction of the sensing platform. We present a two-hop proof of concept implementation, exhibiting end-to-end latencies on the order of tenths of a second, while dissipating on the order of tens of microwatts during periods of inactivity.

Resource interference is a fundamental barrier to realizing predictable wireless embedded systems. We address this problem by (i) partitioning application and communication tasks onto dedicated platforms, and (ii) designing a platform interconnect to facilitate asynchronous message exchange with predictable run-time behavior. We motivate the need for this platform interconnect, termed Bolt, and describe a prototype implementation. Evaluation results indicate that the developed platform interconnect exhibits tightly bounded run-time execution with low jitter, and a negligible resource overhead with respect to state-of-the-art application and communication platforms.

The wireless sensor network community is currently undergoing a platform paradigm shift, moving away from classical single-processor motes toward heterogeneous multi-processor architectures. These emerging platforms promise efficient concurrent processing with energy-proportional system performance. The use of shared interconnects and shared memory for inter-processor communication, however, causes interference in the time, power, and clock domains, which prevents designers from fully harnessing these benefits. We thus designed Bolt, the first ultra-low-power processor interconnect for the compositional construction of heterogeneous wireless embedded platforms. This paper presents the architectural blueprint for interconnecting two independent processors, while enabling asynchronous inter-processor communication with predictable run-time behavior. We detail a prototype implementation of Bolt, and apply formal methods to analytically derive bounds on the execution time of its message passing operations. Experiments with a custom-built dual-processor platform show that our Bolt prototype incurs a negligible power overhead relative to state-of-the-art platforms, offers predictable message passing with empirical bounds that match the analytical ones to within a few clock cycles, and achieves a high throughput of up to 3.3 Mbps.

We demonstrate the capabilities of Bolt, an ultra-low-power processor interconnect for the composable construction of new multi-processor wireless embedded platforms. Bolt provides asynchronous bidirectional communication between two processors with predictable message transfer times. In this way, Bolt solves the resource interference problem inherent in today's wireless embedded platforms, enabling simpler and more robust system designs with minimal resource overhead. Using our Bolt prototype implemented on a state-of-the-art microcontroller, we demonstrate Bolt's composability and decoupling in time, power, and clock domains.