This article presents an adaptive on-off-delay compensation scheme for Ampere-current-level series-series (SS) wireless power receivers (RXs) to enhance both the power conversion efficiency (PCE) and the power delivering capability (PDC). The proposed off-delay compensation is realized by injecting an adaptive offset which is adjusted by sampling the rectified current. The proposed on-delay compensation is realized by inserting adaptive delays which are adjusted by sampling the dead time of the active full-wave rectifier. The proposed scheme was applied in a dual-mode resonant regulating rectifier which was fabricated in 0.18-$\mu $m CMOS technology, and the regulated output voltage was set to 3.3 V. Measurement results demonstrated that the proposed scheme can effectively compensate for the on-off-delay as the RX input AC current varies from 0.7 to 2 A, corresponding to the coil distance varies from 26 to 42 mm. A measured peak PCE of 92.93% was achieved when the load current and coil distance were 0.945 A and 38 mm, respectively. Compared to the cases without delay compensation, the measured RX PDC increased from 495 mW to 1435.5 mW when the coil distance was 26 mm. Additionally, the measured PDC increased from 2557.5 mW to 4075.5 mW when the coil distance was 42 mm.

This paper presents a dual-loop hybrid low-dropout regulator (LDO) to resolve the conflicts between transient response and load capability. At the digital end, a scalable stochastic flash analog-to-digital converter (SF-ADC) performs fast loop control based on Gaussian-distributed input offset voltage ($V_{\text {OS}}$), enhancing load transient response while reducing circuit complexity. In the analog loop, a fully differential error amplifier (EA) is implemented to suppress the nonlinearity of the SF-ADC, resulting in a fine-regulated output with a 1.67mV/A load regulation. Moreover, the SF-ADC and the power gates (PGs) are implemented with digital standard cells only, being free of external clocks and extra calibrations. Fabricated in a 65-nm CMOS process, the proposed LDO achieves 2.5-A maximum load current ($I_{\text {L,MAX}}$) within an active area of 0.127 mm2. Under a 1.3A/0.8ns current up-stepping, the LDO achieves a 3-ns response time, and the measured output droop ($V_{\text {DRP}}$) is 127 mV.

This paper presents an analog front-end (AFE) circuit with marked timing point for pulsed time-of-flight LiDAR that employs either sampling- or event-based timing approach. The proposed AFE adopts a dual-mode structure for its pre-amplifier which can be configured as a charge-sensitive amplifier (CSA) or a gated active load-assisted TIA (GALA-TIA), depending on the intensity of input current. As a result, both the sensitivity and dynamic range (DR) of the AFE have been effectively improved. In addition, the zero-crossing point of the output signal has been marked as the timing point with a built-in pulse shaper, which allows the back-end circuits of LiDAR receiver discriminate the timing conveniently and accurately. The measured input-referred RMS noise current of the proposed AFE is 37 nA. With dual-mode control, a linear output DR of 80 dB and a wide timing DR of 96 dB with walk error no more than ±160 ps have been achieved. For single-shot measurement application, only CSA mode was enabled and the pulse widths of saturated output signals have been measured to compensate the walk errors, which realized a timing DR of 78 dB with accuracy of ±150 ps. The averaged power consumption is 66 mW and the total silicon area is$0.79\times 0.42\,\,mm^{2}$in 0.18-$\mu \text{m}$CMOS process.

In piezoelectric energy harvesting (PEH), utilizing the synchronized switch interface circuits can significantly enhance the energy harvesting capability. Vibration sensing and synchronization are necessary functions for carrying out the synchronized switching actions. Those functions were usually implemented with an external displacement sensor in the early designs, which is not friendly for self-contained applications. This paper proposes a compact time-sharing solution for energy harvesting and vibration sensing by making full use of a modified buck-boost design. The circuit works in a strong discontinuous conduction mode (DCM). It is based on the principle that, under DCM operation, the voltage levels of the piezoelectric source side and the storage side are proportional to the actively switch- on and passively freewheeling intervals, respectively. Compared with the other self-powered synchronized switch PEH solutions, which rely on analog peak detectors, this self-sensing solution not only provides synchronized triggering signals for carrying out the switching actions but also tells more information about the driven vibration, such as its frequency and displacement magnitude. With the detailed vibration information, such a time-sharing solution offers more design convenience towards future multi-functional battery-free IoT applications.

To increase the energy extraction capability and thus improve the power efficiency, it is critical to reduce the energy loss of interface circuit in the energy harvesting (EH) system. The synchronized multiple bias-flip (SMBF) control has been proposed and proved to be highly effective to increase the output power in piezoelectric EH systems. However, many existing designs based on bias-flip suffer from the limitations in real application as the external control or supply are required. Moreover, the control algorithm is often only suitable for a designated transducer and inductor. In this paper, an integrated piezoelectric EH interface circuit with synchronized triple bias-flip (S3BF) has been proposed to flip the voltage across the parasitic capacitor of piezoelectric transducer during the zero-crossing. Meanwhile, the adaptive control of the flipping signal has also been adopted to meet the requirement of different configurations of transducers and inductors. The proposed interface circuit has been designed in 0.18-μm CMOS technology. Without any external control circuit or power supply, it can achieve cold start-up when the external inductances vary from 33 μH to 500 μH. When the external inductance is 50 μH, the simulated flip efficiency is 87.2 %, and the maximum output power is 17.4 μW, which is 3.4 times of the full-bridge rectifier.

This paper presents a low-power All-MOSFET voltage reference implemented on a 0.18-μm standard CMOS technology. In order to improve the temperature coefficient (TC) of voltage reference, a TC compensation technique based on controlling bulk voltage is proposed. The proposed voltage reference achieves a TC of 13 ppm/°C from -40 °C to 125 °C while dissipating a supply current of 70 nA in normal temperature. The line regulation is 0.02%/V when the supply voltage varies from 1.3 V to 2.1 V, and the power supply rejection ratio (PSRR) at 100 Hz is 74 dB due to the cascode current mirror. Moreover, the current mirror can be reconfigured easily so that the output voltage can be trimmed in this design.

In this paper, a low power three-stage CMOS amplifiers with 375x capacitive load (Ci) drivability will be presented. By employing the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively and the physical size of the compensation capacitors is reduced. A local Q-factor control (LQC) loop is introduced to optimize the Q-factor when loading capacitance Cl changes dramatically, which is essential to improve settling performance. Also, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Implemented in standard 0.13-μm CMOS technology, the amplifier can handle 4 pF to 1.5 nF capacitive load with at least 0.88-MHz unity-gain frequency (UGF) while consuming as low as 24.0 μW of quiescent power at 1.0-V supply voltage.

An improved Nauta transconductor, with output resistance for differential-mode output signals insensitive to process and tuning voltage variations, is presented in this paper. Comparing with the classical Nauta transconductor, the proposed transconductor introduces 4 auxiliary inverters only. It can increase the differential-mode output resistance, and keep the common-mode output resistance nearly no changed at the same time. The proposed transconductor has been implemented in a 7th-order transconductance-C (gm-C) band-pass filter (BPF) in a standard 0.18-μm CMOS technology. The proposed filter has achieved a bandwidth of 20 MHz under a 15-MHz center frequency. Monte Carlo simulation results show that with the same tuning voltage range, the gain deviation of the filter with proposed transconductors is reduced 4.4 dB comparing with the counterpart based on classical Nauta transconductors, and the sensitivity of the quality (Q) factor of filter poles to tuning voltage is also significantly reduced. Measurement results show that the pass-band ripple of the proposed filter is reduced 1 dB, and the stop-band attenuation is reduced 8 dB at 30 MHz.

A 1.2-V 42.3-μW three-stage amplifier capable of driving 0.5-to-15-nF capacitive load is proposed. By removing the inner Miller capacitor and adopting cascode Miller compensation in the outer feedback loop, the complex-pole frequency is extended effectively and the size of the compensation capacitors is reduced. Moreover, the Q-factor is reduced by paralleling a small Miller capacitor to the cascode compensation block. Furthermore, the presence of two left-half-plane zeros created by feedforward transconductance stage and cascode Miller capacitor in the proposed topology can improve the stability and slew rate of the amplifier. Implemented in 0.13-μm CMOS technology, the simulated gain-bandwidth product (GBW), slew rate (SR) and phase margin when driving a 15-nF capacitor are 1.13 MHz, 0.16 V/μs and 37°, respectively.

A two-stage large-capacitive-load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain- bandwidth product (GBW). Implemented in a standard 0.13-μm CMOS technology and powered by a 0.7 V supply with a current consumption of 20 μA, the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a capacitive load of 9.5 nF. The average slew rate is 0.3679 V/μs. The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.

A gain and slew rate enhancement technique for amplifiers, based on starving current in static state and feeding excessive current during slewing, is proposed in this paper. Demonstrated in a current-mirror amplifier using a standard 0.18-μm CMOS process, the dc gain is boosted by 15 dB, and the slew rate is enhanced by over 600% compared with a conventional current mirror amplifier and 1100% compared with a current-starved amplifier. In the meanwhile, static power consumption is reduced by more than 2/3 without sacrificing unity-gain frequency, output swing or stability. The total power dissipation is only 63.4 μW under 1.8 V supply.

This paper presents a fixed-frequency auto-buck-boost SIMO dc-dc converter with duty-cycle redistribution and duty-predicted current control. The switching sequence of the power transistors in the power stage and the controller design achieve fixed-frequency operation with an optimized duty-cycle allocation, to deal with static and dynamic unbalanced loading conditions of different channels. The proposed control scheme reduces average inductor current for reducing conduction loss and cross regulation during load transients.

This paper presents three different topologies of energy-efficient fast-transient low-dropout regulators (LDOs) for SoC applications. They include: 1) an output-capacitorless LDO with a direct voltage-spike detection circuit, 2) an output-capacitorless 90-nm LDO compensated by a single Miller capacitor, and 3) a power-efficient 90-nm LDO with multiple small gain stages. The LDO designs demonstrate some recently developed circuit techniques to improve both the regulation accuracy and transient performance. Experimental results are included in this paper to verify the achieved performance.

A fold-back current-limit circuit, with load-insensitive quiescent current characteristic for CMOS low dropout regulator (LDO), is proposed in this paper. This method has been designed in 0.35 mum CMOS technology and verified by Hspice simulation. The quiescent current of the LDO is 5.7 mA at 100-mA load condition. It is only 2.2% more than it in no-load condition, 5.58 mA. The maximum current limit is set to be 197 mA, and the short-current limit is 77 mA. Thus, the power consumption can be saved up to 61% at the short-circuit condition, which also decreases the risk of damaging the power transistor. Moreover, the thermal protection can be simplified and the LDO will be more reliable.