Demo Data from EDBT 2026 / reviewers in the wild / expert
J. Liénard
dblp:71/1133
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1975
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital arithmetic circuits |
0.0 | 1 | 1975 | An Overflow Detection and Correction in Digital Filters · IEEE Trans. Computers 1975 |
Integrated circuit design › digital signal processing circuits
digital filter |
0.0 | 1 | 1975 | An Overflow Detection and Correction in Digital Filters · IEEE Trans. Computers 1975 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1975 | An Overflow Detection and Correction in Digital FiltersabstractA new method for correction of two's, complement adders characteristics at the output of the multiplier following the adders is proposed. It is very suitable to ordinary pipe-line implementation. A. Landauro, J. Liénard |
IEEE Trans. Computers | 2 |