Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a given size. The edges are used to generate fault critical areas which are classified by the list of circuit nodes that are shorted by a defect of a given size falling within that area. These algorithms can be used as a framework on which other critical area algorithms can be generated, notably missing material and pinhole critical generation. The algorithms presented in this paper have the advantage that they are not restricted to Manhattan layout and that they are computationally efficient.

The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples.>