Stochastic computing (SC) is an approximate computing that represents numerical values based on the probability of ones in bitstreams and performs operations probabilistically. Arithmetic circuits for SC (SC circuits) have attracted attention for applications such as machine learning and image processing due to advantages like not only low area and power consumption but also high fault tolerance. To accelerate stochastic computing based on linear finite state machines (FSMs), parallel implementation of linear FSMs has been proposed. The first objective of this paper is to analyze this parallel implementation method and to clarify the details of the design and the cost-effectiveness of the parallel implementation. Through this analysis, it is shown that hardware cost can be significantly reduced while maintaining high accuracy. As the second objective, this paper proposes a new method of parallel implementation using multi-input linear FSMs in order to further improve the accuracy. Experimental results show these proposed designs can achieve high accuracy while keeping the area and delay low.

Video data is essential for performing computer vision applications. However, errors due to noise or soft errors can be significant, potentially rendering the system invalid. Therefore, detecting such errors is important for these applications. In a real-time video stream, there is no golden reference video data to examine video quality during the functional operation of video processing. To address this issue, the no-reference testing method provides a highly attractive solution. In this work, we propose a no-reference test method that extracts error information from the RGB channels in video data. The proposed method improves test accuracy and precision compared to the previous method designed for human vision when applied to object detection. Experimental results show that more than 90% test accuracy and precision can be achieved. The costs incurred by the proposed method are also discussed. Additionally, based on the results, we further discuss setting different criteria for dynamic and static backgrounds of the target video.

Error tolerant applications such as video processing and machine learning can tolerate some kinds of errors in computation. For error tolerant applications, approximate computing, which aims to reduce computational cost and power consumption by omitting a part of computation within the error tolerance, has been attracting attention in recent years. As a kind of approximate computing with logic circuits for error tolerant applications, various approximate multipliers, which can produce approximate products with small hardware cost, have been proposed. Because such approximate multipliers are employed for error tolerant application requiring high reliability, e.g., autonomous systems, the reliability of the multipliers is one of important issues. In this paper, we focus on three types of approximate multipliers with recovery schemes and discuss the reliability of the approximate multipliers. According to fault acceptability, first, we propose a reliability model of approximate multipliers used for error tolerant applications. With this model, we analyze the relationship between the error recovery ability of the approximate multipliers and their reliability, and then discuss the design of approximate multipliers that can maximize their reliability. Experimental results clarify the optimal designs in terms of the reliability under several situations with different fault occurrence probabilities and error tolerance levels.

As one of test methodologies for image processing circuits, a no-reference test scheme based on false-edge detection has been proposed. Because this scheme does not require any reference circuit or reference data to detect faults, it can reduce test cost. In this paper, we discuss an improvement of the false-edge detection for no-reference test scheme. We analyze the misjudged cases by the previous scheme and clarify that the block-based image processing, which is a general way to process images, is one of the reasons of the misjudgment. Based on this analysis, we improve the false-edge detection by extending the definition of the false-edge. Experimental results show that this improvement can enhance the ability of the false-edge detection, so that it can achieve high test accuracy without large computational overhead.

In safety critical systems, e.g., automotive systems, the concept of fail-operational is very important. In this paper we focus on an approximate voting scheme called IDMR (Inexact Double Modular Redundancy), which can detect an error of the output of the duplicated system and correct the error approximately if the significance of the error is within a certain limit; The systems with IDMR can operate continuously even if a fault occurs in the system, i.e., the systems are fail-operational. To enhance the ability of IDMR scheme, we propose an extended architecture for IDMR scheme, which is called E-IDMR (Extended IDMR). The proposed E-IDMR can correct large errors that cannot be corrected by IDMR, so that the systems with E-IDMR achieve higher fail-operational ability than those with IDMR. Application to automotive ABS and LKAS shows that the proposed E-IDMR is more effective for implementation of these fail-operational systems.

Register-transfer level (RTL) scan design aims at optimizing the scan logic as well as the original logic during logic synthesis by modifying a given RTL description to make every register scannable. The modified RTL description, however, is not uniquely determined for realizing the scan functionality, and therefore, one should carefully modify the description because different descriptions with the same functionality can yield different gate level (GL) circuits in terms of area/delay in practice. In this paper, RTL descriptions are presented for constructing intended scan paths that make use of existing RTL modules such as multiplexers (MUXs) and operational units to reduce the area overhead incurred by scan insertion. Such descriptions have been derived from preliminary experiments that extensively analyze the correspondence between a scan description, its structural interpretation in logic synthesis and the synthesized GL circuit. This paper also presents an algorithm for determining scan paths that maximally exploit effective RTL structures where existing MUXs can be utilized for scan path construction with low area overhead. Experimental results show that the proposed algorithm together with structure-aware scan descriptions is effective in reducing area overhead.

Presents the title page of the proceedings record.

Collaborators are required to share a broad range of information in collaborative work. In physical spatial collaboration such as team dancing, theatrical performance, and team sport, one's behavior should be in accord with the partner's; the relative position in distance and in direction is critically important all the time even when moving. To realize remote physical spatial collaboration, achieving the shared recognition of positional relationship is one of the key issues. In this paper, we propose a setup between two remote sites where each collaborator immerses in the other remote site by a telepresence robot situated in the other site. The telepresence robot is a wheeled platform with a camera attached at man's eye height. It moves in response to the remote user's position and orientation and enables the user to get the first-person view video through a head-mounted display. By using two telepresence robots from both sites, both collaborators can recognize the partner being in front of him/her and can grasp the distance and the orientation of the partner in remote site. In the proposed setup, users can grasp the positional relationship as accurate and quick as the existing fixed views including the bird's-eye view.

Real-time keywords potentially demonstrate positive effects when they are provided in cross-cultural communication. Previously real-time keywords generated by a speaker during talking were investigated, and it was found it contributes to build mutual understanding and knowledge. However the use of keywords was not clarified in respect of when and how was typed in real-time communication. In this paper we analyze the data sets of multiple media files and typed materials collected through the experiment, and investigate the use of keyword in a collaborative dialogue. Consequently it was found that speaking was earlier and typing was 2.6 seconds behind of relevant speech, which met the requirement that real-time transcript was beneficial when its shown within 5 seconds. Besides, noun phrases that were typed as keywords were categorized referring to utterance. It was consequently found that 55% of all keywords were expansion and replacement of NS message when speakers got explicit interlocutors acceptance. Lastly conversation analysis was conducted to articulate how keywords are expressed in a conversation. The data showed that speakers uttered multiple episodes when speakers utilized keywords, but briefly uttered in standard manner without keywords.

Stochastic computing (SC), which is an approximate computation with probabilities, has attracted attention owing to its small area, small power consumption and high fault tolerance. In this paper, we focus on the fault tolerance of SC with linear finite state machines (linear FSMs). We show that state assignment of FSMs considerably affects the fault tolerance of FSM-based SC circuits, and present a Markov model representing the impact of the state assignment on the behavior of faulty FSMs. Furthermore, we propose a heuristic algorithm for appropriate state assignment that can mitigate the influence of the transient faults. Experimental results show that the proposed state assignment can significantly reduce the influence of the faults.

Many studies have focused on supporting orchestral performers. In some of these studies, researchers helped multiple players perform without conductors by using a system that conducts the orchestra with artificial, or virtual conductors. Several approaches have been taken in this field. Some conduct players using a conductor made from computer graphics, while others conduct through the changing or moving of figures. However, these studies have not demonstrated how to conduct specific instructions for each player. We propose a group of personalized virtual conductors for a group of players such as an orchestra. To date, the studies of virtual conductors have only addressed a single conductor. However, because the required dynamics, tempo, and nuances are different based on each player's role and part, personalized conduct may be desirable. We developed a prototype that includes a group of personalized virtual conductors and found it has tendency to better for the players and listeners.

A help desk is composed by a customer and a clerk. At a help desk it is important to share information with each other. However, when the customer is more than one person, it is difficult for the clerk to understand the intentions of the customers. In this study, we created a system which can support a travel agency desk. We propose the system to support the clerk to understand the interest degree of multiple customers simultaneously. And our system supports them to decide their travel plan. This system presents the travel information to customers on a tabletop interface, and detects the line-of-sight and the touching actions of the customers. By using the detected data, this system can measure the interest degree of the customers and notify the clerk of the result. In addition, customers can create the travel plan on the tabletop interface with the clerk. When the clerk can provide the best information and guide customers smoothly with this system, planning their itinerary would become easier. We aim to simplify the process necessary at the travel agency desk by using this system.

Supporting effective remote conversation is directly related to effective CSCW. It is often the case that audio is more important than video in remote conversation. Yet most existing remote conversation systems still have simple audio units such as monaural or 2ch stereo output. This is different from face-to-face conversation where different voices come from different locations. Distributed location of multiple voices is considered to make the listening easier but has not been investigated enough. We studied the effects of distributed auditory localization of multiple voices in different locations and in different languages. As a result, it was found that distributed localization is effective in recognizing multiple voices regardless of the languages in both objective and subjective measures.

Reliable built-in self-test (Reliable BIST) scheme equips to be tolerant of faults, which occur in embedded BIST circuits. To realize reliable BIST, it is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a self-error-correctable response analyzer (RA) for a reliable BIST scheme. Experimental results show that test-reliability of SECRA is superior to TMR MISRs on the assumption that transient faults occur in RA during testing CUTs.

In this paper, we focus on fault-acceptability-based logic simplification for error tolerant application. We propose a practical (or cost-effective) logic simplification algorithm. The proposed algorithm (1) avoids acceptability identification for faults that are potentially unacceptable and (2) isolates redundancy identification procedure from acceptability identification. Experimental results show that, compared with a previous algorithm, the proposed algorithm can reduce the computational effort without losing the ability of logic simplification.

This paper discusses a controller design in high-level synthesis to tolerate multi-cycle transient faults under the situation where its datapath has the ability of tolerating such faults. It focuses especially on the control signal generator (or output logic) that is a component of the controller feeding control signals to the datapath in a controller-datapath system, and presents a method of controller synthesis that leverages the error correction/detection ability of the datapath. Experimental results show that the proposed method can synthesize fault tolerant controllers with small area overhead compared with the conventional method based on triple modular redundancy (TMR).

Error tolerant applications can tolerate specific errors, whose frequency and/or severity are within certain limits. This error tolerability is greatly instrumental in simplifying logic circuits for such applications. In this paper, we propose a logic simplification method for error tolerant application. Owing to error tolerance, we have an opportunity to complement several minterms of a given logic function within a threshold; if appropriate minterms are selected to be complemented, the given function can be greatly simplified. To select such minterms, we focus on two transformations, expansion and reduction, of prime implicants of the given logic function, and discuss the effect of the transformations on logic simplification. The proposed algorithm utilizing such transformations can efficiently find effective minterm complement. Experimental results show that, compared with a previous method, which employs only expansion of prime implications, the proposed algorithm can produce smaller logic circuits with reasonable computational effort.

This paper presents the design, implementation, and evaluation of a sports tactics analysis supporting system. In the field of sports, tactics analysis is conducted using data from multiplayer games. In so doing, it is important to recognize the actual play in a sports game. This research focuses on reproducing player action in sports games. Unlike the conventional systems that only display static images of the players, this proposal system shows the player moving in a manner similar to a game in virtual space that reproduces the pitch, so user is able to have realistic image of game, and therefore the user acquires proper spatial information. The system also allows the user to move the object by touching a display. Consequently, it provides an environment in which users can easily discuss the game. From experiments, we confirmed the system facilitates users in tactics analysis.

Stochastic computing, which is an approximate computation with probabilities (called stochastic numbers), draws attention as an alternative method of deterministic computing. In this paper, we discuss a design of compact and accurate stochastic circuits. Stochastic circuits are known as a way to stochastically compute complex calculation at low hardware cost, while stochastic number generators (SNGs), which are used for converting deterministic numbers into stochastic numbers, account for a large fraction of the circuits. To reduce such SNGs in stochastic circuits, we propose a technique to share random number generators with several SNGs. This sharing method employs circular shift of the output of LFSRs to reduce the correlation between stochastic numbers. We also discuss the influence of input correlation around a multiplexer, which is a scaled adder for stochastic computing, so as to avoid over reducing the input correlation. Application of the proposed techniques to two stochastic image processing shows the reduction in the size of SNGs without greatly sacrificing accuracy.

Reliable built-in self-test (Reliable BIST) is a scheme in which embedded circuits used for self-testing circuits-under-test (CUTs) are designed to be tolerant of their faults. Reliable BIST is especially important for highly reliable on-line testing for real-time system, reliable BIST is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a transient fault tolerant test pattern generator (TPG) for a reliable BIST scheme. The proposed TPG, called EC-TPG, can correct (or mask) errors that occur on itself during testing CUTs, so that it can enhance its test-reliability, which is the probability that the TPG can generate correct (expected) test patterns. We analyze the test-reliability of EC-TPG in order to show that EC-TPG has high test-reliability. Furthermore we demonstrate that, in on-line BIST for real-time systems, EC-TPG can achieve higher test-reliability compared with a test re-execution scheme with error detection through some case studies.

Dining with a remote person requires that both participants are available at the same time to eat together. Because of time-zone differences and other such contingent factors, this condition can often be hard to fulfill. One solution may lie in time-shifted communication. A person can enjoy a meal while watching an earlier recorded video of a remote person's dining. However, in a time-shifted environment, achieving dining synchronization is a challenge. In this research, we propose a time-shifted tele-dining system (KIZUNA) enabling people to enjoy a meal together in a virtual environment. The system adapts the displayed video's playback speed to the difference in dining progress between the local and remote person. This is likely to enhance communication and increase enjoyment while dining. A validation experiment revealed that the proposed KIZUNA adaptation method enhanced diners' communication behavior, and significantly enhanced the perceived presence of the remote person, in comparison with conventional time-shifted tele-dining. This result suggests a promising future for the KIZUNA system.

This paper presents the design, implementation, and evaluation of an interactive tabletop and vertical touch screen system that supports recognition of virtual soccer field. Arrangement player positions, imagine the sense of distance between players, such task is difficult for inexperienced people, because they need to imagine real field space in detail. To get proper spatial information and solve this problem, this research focuses on two viewpoints, an overhead view and a first-person view. The proposed system shows both viewpoints, using the tabletop display for the overhead view and the vertical display for the first-person view. From experiment that verified effectiveness for visualizing the game space, We confirmed the system allows the user to intuitively move objects in each viewpoint, and promotes the image of game situations than conventional systems.

Pair programming , a programming technique conducted by two programmers work together at one work station, has been adopted for learning programming. Although it is known to be effective in various aspects, micro observation of the learning activity, collaboration, has yet to be conducted in relation to the outcome. In this study, behavior in pair programming learning was investigated in terms of verbal communication and programming action, and was compared in relation to the success of problem-solving. Findings are that, in the successful cases, 1) the learners took programming actions more frequently, and 2) the learners took more programming actions immediately after the dialogue. From this, it is suggested that closely-knit dialogue and action can be an indicator of successful problem-solving, and the findings can be applied to a collaborative learning support systems.

Videoconferencing environment is one of the most popular ways of connecting remote people. To achieve conveyance of realistic sensation through its video image is one of the major goals. One way to implement highly realistic image is to use life-size scale image of a remote person which is presented by a large display. However at the same time, the large display hides a large area from the local person's front view and replaces it with other remote side's background. This might decrease the person's full surrounding awareness. To solve these conflicting effects of the large display, we propose extracting remote person's figure from his/her background and superimposing him/her over local person's front view. In this way, the local person feels as if the remote person exists in front of him/her in his/her spatial environment. In this paper, we describe the design and implementation of such a system and the preliminary experiment. The initial result of the experiment suggested that the proposed system achieved high realistic sensations, increased the local surrounding awareness, and minimized the remote background's distraction compared with a conventional videoconferencing system.

Many test designs (or DFTs: designs-for-testability) have been proposed to overcome various issues around LSI testing. In this paper, we propose a cost and benefit model for comparing several test designs in terms of the final profit of logic LSI design and manufacturing. Test designs can affect chip area, testing time, test generation time and fault coverage; in the proposed model, we clarify the relationship among these factors for major three test designs: scan design, built-in self-test (BIST) design and test compression design. The proposed model reveals the final profit for each test design in a given LSI design and manufacturing environment, so that it can designate a suitable test design in the early stage of LSI design flow. We show an example of application of the proposed model for test design selection in a given environment.

Theater is a collaborative art form that involves production team members with different specialties. Because theater involves various technical elements, such as stage design and lighting, the production team must work in cooperation among various departments to design a theatrical production. When planning a theatrical production, it is difficult to visualize the stage as a whole and to incorporate the ideas of production team members from various departments. In this paper, we propose a system for reproducing the theatrical stage by means of a virtual stage linked to a physical miniature stage. The miniature stage is presented on a tabletop interface, and the virtual stage is created by computer graphics to reflect the actions on the miniature stage in real time. By actually presenting theatrical production ideas in two spaces, users can more easily collaborate and gain a comprehensive view of the stage.

During a mealtimes, we usually enjoy not only eating itself but also having a conversation with other people together. Having a meal with our family or close friends is so enjoyable and an easy task because we already know each other. However we also have a chance to eat with acquaintances or totally new persons. In these cases, it is thought that the conversation would be difficult to continue because of the lack of common conversation topics. In this research we propose the Communication Supporting FDT (Future Dining Table) to solve the communication problem. The proposed system can detect the person who does not participate in the conversation while eating and help the person start the conversation by displaying the news information on the dining table.

Test compression / decompression is one of effective methods for testing today's VLSI. In this paper, we discuss test compression with image compression algorithms, e.g., JPEG algorithm. Image compression algorithms can not only achieve considerably high compression but also require no additional decompression circuity on a chip under test if the chip includes image decoders. Moreover, we propose a method for generating seeds (or compressed test data) in the case where a JPEG decoder is utilized as a test decompressor. Although JPEG algorithm carries out lossy compression, given a test data, the proposed algorithm can search seeds that can be decompressed to another test data preserving the test quality of the given test data, and produce a small set of seeds with high fault coverage. Experimental results show the proposed method can achieve compression ratio comparable with several previous test compression methods without larger hardware overhead.

It is known that a virtual teacher-model's position and orientation influence (a) the number of errors, and (b) the accomplishment time, in physical-task learning using mixed reality (MR) environments. This paper proposes an automatic method to adjust the virtual teacher's orientation according to a given task motion. Through always showing the physical task's critical features regardless of changes in position, mimicking errors regarding the respective task are expected to be minimized. Thus this research is considered to advance transferring skills of physical tasks. It can also be applied to remote collaborative work.

It is known that a virtual teacher-model's position and orientation influence (a) the number of errors, and (b) the accomplishment time, in physical-task learning using mixed-reality environments. This paper proposes an automatic adjustment method of the virtual teacher's rotation angle so that the learner can observe the important body motion easily. The method divides the whole task motion into fixed duration segments, seeks the most moving part of the body in each segment, and rotates the virtual teacher to show the most important part to the learner accordingly. To test the method, a generic physical task learning experiment has been conducted. The method was revealed to be effective to the motion that gradually changes the most moving part such as manufacturing and cooking tasks.

As the advance in semiconductor technology, the tolerance for transient faults caused by particle strike, called SET (single event transient), becomes an important issue, and moreover future technologies bring the possibility of occurrence of long duration errors spanning across multiple cycles of the circuits due to particle strike. In this paper we discuss high-level synthesis for multi-cycle transient fault tolerant datapaths. Clarifying the conditions for multi-cycle error correctability and detectability of multi-cycle transient fault tolerant datapaths, we propose a heuristic algorithm for finding optimal operator binding of kc-cycle error correctable / kd-cycle error detectable datapaths with minimum operators. The method focuses on only transient faults (not permanent ones), and therefore it can derive appropriate designs necessary and sufficient for tolerance of SET avoiding use of excessive hardware resources.

The tabletop dish recommendation system that recognizes the user's dining activity in real time has been developed. The system displays recommendations over the table to the existing dishes. This paper presents the investigation of the display positions of the recommended dish. Three display positions to the existing dishes were investigated. The position adjacent to the existing dishes and the culturally natural position were better evaluated than the random position.

The hybrid delay scan design in which some flip flops (FFs) are controlled as skewed-load FFs and the others are controlled as broad-side FFs was proposed. Noticing that the hybrid delay scan design potentially has a capability of two test application modes: one is the broad-side test mode, and the other is the hybrid test mode, we present a hybrid test application of the two test modes in the hybrid delay scan design. In addition, we also address a way of skewed-load FF selection based on propagation dominance of FFs in order to take advantage of the hybrid test application. Experimental results for ITC'99 benchmark circuits show that the proposed hybrid scan design with the hybrid test application can achieve higher fault coverage than the previous hybrid scan design.

Fail-soft systems with reconfigurable devices, which recover themselves by repeating isolation of faulty portions with graceful degradation, have been proposed. In this paper, we proposed a fail-soft system on an FPGA and discuss the performance and availability of the system. The proposed system can infer the type of faults from obtained errors, and then adaptively reconfigure itself autonomously, so that it can achieve high availability while keeping high performance. Case studies show that the proposed system can achieve high availability with high performance by avoiding excessive recovery.

Enhancement of dining environment by information technology is explored in this paper. A table system to recommend additional dishes according to the dining status is introduced. By modeling dining behavior as the sequence of eating, dining status is estimated from the history of bites. The system recognizes the user's dining activity in real time, and stores its history. It is expected to be useful in the environment where additional dishes are often ordered such as a pub. By iterative design, the hand recognition method in the system was changed from the use of a visual marker in the first prototype to image processing in the current prototype. Evaluation was conducted to show the improvement of the recognition.

In this paper, we propose a method for identifying false paths based on functional unsensitizability of path delay faults. By using RTL structural information, a number of gate level paths are bound into an RTL path and the bundle of them can be identified in a reasonable amount of time. The identified false paths are useful for over-testing reduction caused by DFT techniques, such as scan design, and also area and performance optimization of circuits during logic synthesis. Experimental results show that our proposed method can identify false paths in a few seconds for several benchmarks.

Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancement of LSIs and selective hardening for LSI systems. In this paper, we propose test generation models for threshold test generation. Using the proposed models, we can efficiently identify acceptable faults and generate test patterns for unacceptable faults with a general test generation algorithm, i.e., without a test generation algorithm specialized for threshold testing. Experimental results show that our approach is practically effective.

A register-transfer level (RTL) circuit meeting a design specification may contain some functionally unused paths.If functionally unused paths can be easily identified at RTL,the information can be utilized to eliminate the corresponding gate-level paths from the target of testing.Testing such gate-level paths is considered to be futile. In this paper, we present a method for identifying such functionally unused paths, called RTL don't care paths, using RTL information, and a method of synthesis for transforming the identified paths into untestable paths which will never do a mischief.As a result, our approaches contribute to identification of many untestable paths and reduction of over-testing.

Test data compression /decompression schemes for testing SoCs can reduce test application cost. A drawback of the previous schemes, however, is that a decompressor must be embedded in an SoC under test. In this paper, we target the testing of SoCs with multimedia cores and introduce a scheme of test compression / decompression with the decoding function in the multimedia cores. This scheme can utilize the decoder and encoder in a multimedia core for compressing and decompressing test data, and consequently it requires slight hardware overhead. As an example of the proposed scheme, we focus on a lossless variable-length coding (VLC) in the JPEG algorithm, and propose a test compression / decompression method using the VLC decoder. We also propose a test generation method for this scheme. Experimental results show that the test compression with the VLC can achieve high compression ratio and the proposed test generation method can increase the compression ratio.

This paper proposes a self-test method of dynamically reconfigurable processors (DRPs) without area overhead. This method constructs a test frame of processor elements (PEs) such that it consists of test pattern generators, response analyzers and PEs under test, and switches several test frames dynamically so as to test all the PEs. Since the number of contexts and test application time are subject to the structure of test frames, we design several test frames with different structures and discuss the relationship of the structures to the number of contexts and test application time. Based on this discussion, we can construct the best test frame according to a given test environment.

We have developed a content construction system for collaborative learning based on a Wiki, a Web- based collaborative document authoring system. Requirements for such a tool are explained in three aspects (usability, content construction, easy and secure operation) and implemented accordingly. Experiment on usability of the system interface suggested improvement from a common Wiki.

We present a graph model and an ILP model for optimal TAM design for transparency-based SoC testing. The proposed method is an extension of (Chakrabarty, 2003) so that not only the system-level cost but also the core-level cost can be simultaneously taken into consideration during the optimization process. We also relax the constraints by considering test dataflows and extend it to be able to handle the case where cores cannot be made transparent due to IP protection. The proposed ILP model can represent various problems including the same problem as (Chakrabarty, 2003) and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to (Chakrabarty, 2003).

Test compression / decompression method using variable length coding is an efficient method for reducing the test application cost, i.e., test application time and the size of the storage of an LSI tester. However, some coding imposes slow test application, and consequently it requires large test application time in spite of its high compression. In this paper, we clarify the fact that test application time depends on the compression ratio and the length of codewords, and then propose a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the length of the cord words to the test environment. Experimental results show that the proposed method can archieve small test application time while keeping high compression ratio.

Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functions by improving an existing test plan generation algorithm based on strong testability. Experimental results show that the proposed algorithm is effective in reducing additional hold functions, i.e., reducing hardware overhead and delay penalty of datapaths.

This paper describes a technique for mapping objects such as insects and plants in the field on a blank map in mobile learning. We propose map creating system that utilizes man's subjective geographic recognition in addition to a GPS. With the help of man's ability of recognizing placement of objects and geographical relations between objects, objective geographic information with small error given by a GPS is effectively compensated.

The paper uses the concept of time expansion model (Innoue et al., 2000) to find the test generation for acyclic sequential circuits. It identifies a class of sequential circuits called as max-testable sequential circuits, where test generation can be obtained using a combinational test generator with the capability of detecting multiple faults on a kernel of combinational circuit. Any acyclic sequential circuit without hold registers belongs to this class. For the sequential circuits having hold registers, a subset of such circuits is found to be belonged to max-testable class. The paper also suggests an algorithm to find such class of circuits.

Test compression/decompression scheme using variable-length coding, e.g., Huffman coding, is efficient in reducing the test application time and the size of the storage on an LSI tester. In this paper, we propose a model of a decompressor with a buffer for variable-length coding and discuss its property. The embedded buffer allows the decompressor to operate at any input and output speed without a synchronizing feedback mechanism between an ATE and the decompressor. Moreover, we propose a method for reducing the size of the buffer embedded in the decompressor. Since the buffer size depends on the input order of test vectors, test vector reordering can reduce the buffer size. The proposed algorithm is based on fluctuations in buffered data for each test vector. Experimental results show a case where the ordering algorithm can reduce the size of the buffer by 97%.

Test compression/decompression is an efficient method for reducing the test application cost. In this paper, we propose a response compression method based on Huffman coding. The proposed method guarantees zero-aliasing because faulty responses are mapped into code words, not just fault-free ones. Moreover, the method is independent of the fault model and the structure of a circuit-under-test, and uses only the knowledge of the fault-free responses corresponding to a given test input set. Experimental results of the compression ratio and the size of the encoder for the proposed method are presented.

Acyclic partial scan design is an efficient DFT method. This paper presents a scheduling method for reducing the number of scan registers for an acyclic structure. In order to estimate the number of scan registers during scheduling, we propose provisional binding of operational units, and show a force-directed scheduling algorithm with the provisional binding. Experimental results show that the number of scan registers in the resulting RTL datapaths can be reduced by our method combined with the binding algorithm for acyclic partial scan.

Test compression/decompression is an efficient method for reducing the test application cost. In this paper we propose a test generation method for obtaining test-patterns suitable to test compression by statistical coding. In general, an ATPG generates a test-pattern that includes don't-care values. In our method, such don't-care values are specified based on an estimation of the final probability of 0/1 occurrence in the resultant test set. Experimental results show that our method can generate test patterns that are able to be highly compressed by statistical coding, in small computational time.

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e., the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can also be performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

Test sequences for acyclic sequential circuits can be generated using a time expansion model. The test sequences have features that: (1) the length of each test sequence for each target fault is uniform, and (2) positions of 'don't cares' (X) of each test sequence for each target fault are independent of any target fault. In this paper, focusing on the features, we present two test sequence compaction methods: static compaction and dynamic compaction. The static test sequence compaction method uses a template. The dynamic test sequence compaction method uses a reverse transformation fault simulation: a fault simulation for a time expansion model with test patterns into which test sequences are reversely transformed after the static compaction. Experimental results for some acyclic sequential circuits show that the compaction methods reduce the number of test patterns by 66% to 81%.

This paper presents a high-level synthesis method for testable data paths with partial scan design based on acyclic structure. For a given scheduled data flow graph, we propose a heuristic method of operational unit binding and register binding to minimize the number of scan registers for acyclic structure without sacrifice of area overhead.

In this paper, we theoretically and experimentally show the effectiveness of partial scan design based on internally balanced structure, which is a sequential circuit capable of generating tests with a combinational test generation algorithm. Moreover, we introduce a method of extended partial scan design, which replaces part of not only flip-flops by scan flip-flops but also wires by bypass flip-flops in a sequential circuit, and propose a method of extended partial scan design based on internally balanced structure. Experimental results for benchmark circuits show that the proposed partial scan design and extended partial scan design can be implemented with low area overhead.

We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We performed experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scan while preserving almost 100% fault efficiency.

In this paper, we introduce universal fault diagnosis such that when applied to an unprogrammed FPGA, it locates a fault in any faulty programmed FPGA corresponding to the unprogrammed FPGA. If a faulty part in an FPGA can be identified prior to programming it, we can implement a required logic function on the fault-free part by isolating the faulty part. Then, we propose a universal fault diagnosis procedure that locates a faulty CLB in a look-up table FPGA. The complexity of the universal diagnosis procedure for FPGAs with block-sliced loading is independent of its array size, i.e., C-diagnosable.

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.

The test generation problem for a sequential circuit capable of generating tests with combinational test generation complexity can be reduced to that for the combinational circuit formed by replacing each FF in the sequential circuit by a wire. In this paper, we consider an application of this approach to general sequential circuits. We propose a test generation method using circuit pseudo-transformation technique: given a sequential circuit, we extract a subcircuit with balanced structure which is capable of generating tests with combinational test generation complexity, replace each FF in the subcircuit by wire, generate test sequences for the transformed sequential circuit, and finally obtain test sequences for the original sequential circuit. We also estimate the effectiveness of the proposed method by experiment with ISCAS'89 benchmark circuits.

Article Integration of face-to-face and video-mediated meetings: HERMES Share on Authors: Tomoo Inoue Department of Information and Computer Science, Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 Japan Department of Information and Computer Science, Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 JapanView Profile , Ken-ichi Okada Department of Information and Computer Science, Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 Japan Department of Information and Computer Science, Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 JapanView Profile , Yutaka Matsushita Department of Information and Computer Science, Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 Japan Department of Information and Computer Science, Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 JapanView Profile Authors Info & Claims GROUP '97: Proceedings of the international ACM SIGGROUP conference on Supporting group work: the integration challengeNovember 1997 Pages 405–414https://doi.org/10.1145/266838.267361Online:16 November 1997Publication History 10citation465DownloadsMetricsTotal Citations10Total Downloads465Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Initialization of sequential circuits is one of time-consuming processes in test generation for sequential circuits, and hence synthesizing sequential circuits of which synchronizing sequences are short is an important approach to reducing the cost of test generation for the circuits. In this paper, we propose an approach to the synthesis of finite state machines (FSMs) with partial scan. We focus on repeating partial scan for synchronizing FSMs, and present an extended synchronizing sequence which consists of scan inputs and normal inputs, and which takes a circuit to a single specific state, regardless of the initial state. To synthesize synchronizable FSMs, we formulate a problem of minimizing extended synchronizing sequence length, and present a heuristic algorithm for the problem. We show the experimental results of the minimization of extended synchronizing sequence length on MCNC'91 benchmark FSMs. The experimental results show that the proposed heuristic algorithm can find a minimum-length extended synchronizing sequence for most of MCNC'91 benchmark FSMs, and the length of the extended synchronizing sequence is three or less for all the benchmark FSMs.

In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity.

A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.

The paper deals with nonverbal communication in asynchronous networks. It is well known that nonverbal communication plays an important role in interpersonal communication. However, nonverbal communication has not been used in traditional character based network communication until now, yet the need for conveying feelings has increased. Due to the development of multimedia networks, it is thought that nonverbal communication can be valuable for network communication. The research is based on the importance of expressing feelings through nonverbal communication, especially gestures. It has not yet been determined what kind of feelings can be conveyed by gestures so the evaluation of feelings expressed by gestures has been done using animated cartoons. From this, it has been shown that feelings expressed by gestures on display are distinguished in five ways by the Japanese. Furthermore, an evaluation of electronic mail with computer graphics animation has been done as an example of asynchronous network communication. From this, it has been seen that mail with the gestural animation reflects the feelings of its animation. Using gestural animations to convey feelings in asynchronous networks has been suggested.>

Article Free Access Share on Learning from TV programs: application of TV presentation to a videoconferencing system Authors: Tomoo Inoue Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 Japan Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 JapanView Profile , Ken-ichi Okada Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 Japan Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 JapanView Profile , Yutaka Matsushita Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 Japan Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama 223 JapanView Profile Authors Info & Claims UIST '95: Proceedings of the 8th annual ACM symposium on User interface and software technologyDecember 1995 Pages 147–154https://doi.org/10.1145/215585.215967Published:01 December 1995Publication History 25citation450DownloadsMetricsTotal Citations25Total Downloads450Last 12 Months20Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The order of faults which are targeted for test-pattern generation affects both the processing time for test generation and the number of test-patterns. This order is referred to as a test generation schedule. In this paper, we consider the test generation scheduling problem which minimizes the cost of testing. We analyze the effect of scheduling based on test-pattern generation time and dominating probability. Then, we present experimental results on the ISCAS'85 benchmark circuits.

Client-Agent-Server model (CAS model) which can decrease the work load of the client by adding agent processors to the Client-Server model (CS model) is proposed and an approach to parallel test generation for logic circuits on the CAS model is presented. Two problems are considered: optimal granularity problem and optimal scheme problem. First, the problem of parallel test generation on the CAS model is formulated to analyze the effect of the granularity (grain size of target faults allocated to processors) in both cases of static and dynamic task allocation (optimal granularity problem). Then the relationship between the number of processors and the total processing time is analyzed (optimal scheme problem). From the analysis, it is shown that the CAS model can reduce the total processing time over the CS model and that there exists an optimal scheme (an optimal pair of numbers of agent processors and server processors) for the CAS model which minimizes the total processing time for a given number of processors. To corroborate the analysis, the proposed parallel test generation algorithm is implemented on a network of more than 100 workstations and experimental results for the ISCAS benchmark circuits are presented. It is shown that the experimental results are very close to the theoretical results which confirms the existence of optimal granularity and optimal scheme which minimizes the total processing time for the CAS model.>

The problem of test generation for logic circuits is known to be NP-hard, hence it is very difficult to speed up the test-generation process due to its backtracking mechanism. An approach to parallel processing of test generation for logic circuits in a loosely coupled distributed network of general-purpose computers is presented, and the effects of allocating target faults to processors, the optimal granularity (grain size of target faults), and the speed up ratio of the multiple processor system compared with a single processor system are analyzed.>

The problem of test generation for logic circuits is known to be NP-hard, and hence it is very hard to speed up the test generation process due to its backtracking mechanism. The authors present an approach to parallel processing of test generation for logic circuits in a loosely coupled distributed network of general-purpose computers. They analyze the effects of the allocation of target faults to processors, the optimal granularity (grain size of target faults), and the speedup ratio of the multiple-processor system to a single-processor system. To analyze the case in which a test pattern generated for one fault can also be a test pattern for other faults if fault simulation is performed, they introduce a ratio of newly processed faults to target faults and derive the expressions of optimal granularity in cases of both static and dynamic task allocation. They also derive an expression of the speedup of a multiple-processor system in the homogeneous case. The analysis indicates that the speedup approaches N, the number of servers, if the data transfer time per fault and the waiting time per communication are much smaller than the processing time per fault and if the decrease ratio of newly processed faults due to overlapped processing is much smaller than the ratio of newly processed faults.>