Demo Data from EDBT 2026 / reviewers in the wild / expert
Garold S. Tjaden
dblp:71/1874
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1973
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 54% High-performance computing · 46% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
High-performance computing › sparse linear algebra
matrix ordering |
0.0 | 1 | 1973 | Representation of Concurrency with Ordering Matrices · IEEE Trans. Computers 1973 |
Processor architecture and microarchitecture
instruction-level parallelism |
0.0 | 1 | 1970 | Detection and Parallel Execution of Independent Instructions · IEEE Trans. Computers 1970 |
Processor architecture and microarchitecture
instruction scheduling |
0.0 | 1 | 1973 | Representation of Concurrency with Ordering Matrices · IEEE Trans. Computers 1973 |
Processor architecture and microarchitecture › superscalar processor
superscalar issue |
0.0 | 1 | 1970 | Detection and Parallel Execution of Independent Instructions · IEEE Trans. Computers 1970 |
Methods — techniques the papers use, named apart from their topics
linear algebraic operations · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1973 | Representation of Concurrency with Ordering MatricesabstractA formal technique for the representation of tasks such that the potential concurrency of the task is detectable, and hence exploitable, during the execution of the task is described. Instructions are represented as a pair of binary vectors d and ê which completely describe the sources and sinks specified by the instruction. Tasks are represented as square matrices M called ordering matrices. The values of the elements of these matrices are used to dynamically indicate the necessary ordering of the execution of instructions. It is shown how several different types of ordering matrices, each type having the capability of exhibiting different amounts of potential concurrency, can be calculated from the d and ê vectors of the instructions of a task using ``linear algebraic-like'' operations. For example, intercycle independencies can be detected with a ternary ordering matrix. This matrix can be extended to dynamically detect opportunities for reassigning the resources specified by certain instructions to increase the amount of potential concurrency. Experimental results are presented showing the relative capability of each of these matrix types for exhibiting potential concurrency. These techniques are shown to produce somewhat greater amounts of potential concurrency than other known dynamic techniques. However, the amounts of potential concurrency found are less than those reported for preprocessing detection techniques. Garold S. Tjaden, Michael J. Flynn |
IEEE Trans. Computers | 1 |
| 1970 | Detection and Parallel Execution of Independent InstructionsabstractFor a single instruction stream–single data stream organization the problem of simultaneously issuing several instructions is studied. Garold S. Tjaden, Michael J. Flynn |
IEEE Trans. Computers | 1 |