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Yirong OuYang

dblp:71/2745 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Reconfigurable computing and FPGAs · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › VLSI testing
FPGA logic block testing		 0.112005
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only) · FPGA 2005
Electronic design automation
hardware verification and test		 0.112005
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only) · FPGA 2005
Electronic design automation › hardware verification and test
test generation		 0.112005
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only) · FPGA 2005
Reconfigurable computing and FPGAs › FPGA architecture
configurable logic block		 0.012005
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only) · FPGA 2005

Methods — techniques the papers use, named apart from their topics

greedy configuration-generating algorithm · 0.1
YearPublicationVenuePosition
2005 A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only)
abstract
This paper presents a new universal test approach for FPGA logic resources. It includes a new greedy configuration-generating algorithm, and a new FPGA Configurable Logic Block (CLB) test model. The model is based on two directed graphs: a structure graph and a configuration graph, which convey the important information from the CLB gate level circuit to the greedy configuration-generating algorithm, so the algorithm can generate minimum the number of test configurations to achieve a given fault coverage. With this new approach, researchers can easily get test patterns optimized both in test time and fault coverage for different FPGA architectures. At the end, we compare experiment results with other test approaches, and the results show test pattern from the new approach is even more efficient than pattern from manual optimization. It also proves that the approach can deal with different types of FPGAs very well.
Yirong OuYang, Jiarong Tong
 FPGA1