Demo Data from EDBT 2026 / reviewers in the wild / expert
B. Chatterjee
dblp:71/2795
· DBLP profile ↗
8ranked-venue papers
0as first author
0since 2021 · last 1991
0000-0002-1293-4068ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 3Graphics, computer vision, multimedia, augmented reality and games · 2Systems, architecture and hardware · 1Databases, data management, data science and information retrieval · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 91% Performance modeling and evaluation · 5% Interconnection networks and networks-on-chip · 4% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
circuit simulation |
0.0 | 2 | 1986 | Compact Modified Nodal Approach for Switched-Capacitor Network Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1986 On the modified nodal approach to network analysis · Proc. IEEE 1985 |
Electronic design automation › circuit simulation › numerical methods for circuit simulation
modified nodal analysis |
0.0 | 2 | 1986 | Compact Modified Nodal Approach for Switched-Capacitor Network Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1986 On the modified nodal approach to network analysis · Proc. IEEE 1985 |
Electronic design automation › circuit analysis
analog circuit analysis |
0.0 | 1 | 1986 | Compact Modified Nodal Approach for Switched-Capacitor Network Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1986 |
Electronic design automation › circuit simulation › analog circuit simulation
switched-capacitor network analysis |
0.0 | 1 | 1986 | Compact Modified Nodal Approach for Switched-Capacitor Network Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1986 |
Performance modeling and evaluation › statistical analysis
sensitivity analysis |
0.0 | 1 | 1986 | Compact Modified Nodal Approach for Switched-Capacitor Network Analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1986 |
Interconnection networks and networks-on-chip
switching network |
0.0 | 1 | 1985 | On the modified nodal approach to network analysis · Proc. IEEE 1985 |
Methods — techniques the papers use, named apart from their topics
cutset analysis · 0.0compact MNA formulation · 0.0matrix reduction · 0.0cutset reduction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | A formal power series approach to the construction of minimal fuzzy automata
B. Chatterjee, Arun K. Majumdar |
Inf. Sci. | 2 |
| 1989 | Segmentation of fingerprint images - A composite method
B. M. Mehtre, B. Chatterjee |
Pattern Recognit. | 2 |
| 1987 | Segmentation of fingerprint images using the directional image
B. M. Mehtre, N. N. Murthy, Surendra Kapoor, B. Chatterjee |
Pattern Recognit. | 4 |
| 1987 | Edge Detection in fingerprints
M. R. Verma, Arun K. Majumdar, B. Chatterjee |
Pattern Recognit. | 3 |
| 1986 | Compact Modified Nodal Approach for Switched-Capacitor Network AnalysisabstractA method based on cutset analysis is presented to compact the network matrices written in the modified nodal formalism. Operational amplifier models with finite as well as infinite gain have been used. Simple algorithms for frequency response and sensitivity analyses based on these compact MNA equations are presented. The algorithms have been tested on a small 8086 based system. U. V. Wali, Ranendra N. Pal, B. Chatterjee |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1985 | On the modified nodal approach to network analysisabstractAn algorithm to reduce the size of MNA matrices for switched and nonswitched networks is proposed through the use of cutsets. The procedure is simple and eliminates all diagonal zeros. Closed switches and EMF sources are handled identically. The final size of the matrix may be reduced to the number of nodes when no current-controlled elements are present. U. V. Wali, Ranendra N. Pal, B. Chatterjee |
Proc. IEEE | 3 |
| 1982 | Fixed-point error analysis of rectangular transformabstractThe fixed-point error analysis of long length RT's is presented assuming sign-magnitude or 1's complement arithmetic. The errors introduced by the input-addltion, multiplication and the output-addition stages are separately considered in each dimension and are suitably combined to give the average output noise variance. The various error components signifying the characteristics error parameters of a module are obtained for each short length RT. Filters of different transform lengths are chosen for illustration. The theoretical noise variance obtained in each case is found to have excellent agreement with the corresponding simulated results. The noise performance of RT and FFT filters is also compared. It is seen that the input noise has worsened by a factor of 3.8 bits in passing through an RT filter compared to 6.15 bits as in case of FFT filter. Ganapati Panda, Ranendra N. Pal, B. Chatterjee |
ICASSP | 3 |
| 1981 | Fixed-point error analysis of Winograd basic DFT algorithms considering correlation between noise sourcesabstractRecently, Patterson and McClellan [1] have carried out the fixed-point error analysis of winograd Fourier transform algorithm assuming noise sources to be uncorrelated and have derived expressions for output NSR (noise to signal ratio). Such an assumption is not quite valid. A theoretically revised expression without making such an assumption has been obtained in case of Winograd short-length DFT algorithms. This involves the computation of correlation coefficients among noise sources. The revised results are verified by computer simulations and are found to be in close agreement with those predicted by Patterson and McClellan. It is, in general, observed that the basic modules introduce errors higher than those of FFT and require maximum of half a bit to maintain the same degree of precision. Ganapati Panda, Ranendra N. Pal, B. Chatterjee |
ICASSP | 3 |