Due to their scalability and energy efficiency, memristor-based analog neuromorphic chips (MANCs) have significant advantages in edge computing. Researchers use software to train network parameters, then in hardware deployment, weights are translated into memristor conductances and biases are provided by digital-to-analog converters (DACs). Analog operational amplifiers are utilized for neural signal summation. Nowadays, efficient design, training, and implementation of MANCs have not been thoroughly explored. Particularly, MANC co-design considering software training and hardware deployment has not been studied. To address this issue, we propose Constraints-Aware Training (CAT), which includes hardware constraints of memristor devices, operational amplifiers, and DACs in the training process, thereby enabling co-design between offline training and hardware deployment. To evaluate the proposed methodology, a 4-layer fully connected network (FC-4) and a convolutional network (LeNet-5) are trained by CAT on MNIST and CIFAR-10 datasets, and then deployed in hardware circuits. Experimental results demonstrate that incorporating hardware constraints during offline training through CAT enables convenient and successful MANC hardware solutions.

Despite the immense performance improvement of deep learning-based object detection, the state-of-the-art object detection systems are still prone to misdetections. This work presents a method to predict such misdetections at run-time by using a small network, referred to as ConsensusNet, to learn the correlation patterns or consensus of neighboring detections before non-maximum suppression (NMS). Based on such correlations, ConsensusNet predicts if there are misdetection failures. The proposed method is experimentally evaluated considering single person class from COCO dataset and using YOLOv3 as the object detection system. It shows the proposed method can achieve accuracy of 84.6% and the performance measured in other metrics are also promising. To the best of our knowledge, ConsensusNet is the first network reported for predicting misdetections in object detection.

This paper presents a novel time and voltage based technique for successive approximation register (SAR) analog-to-digital converter (ADC) to improve the conversion speed. By taking advantage of the fact that at low supply voltage there will be a significant difference in comparator decision time for different input voltages, the proposed technique creates multiple auxiliary voltage levels for comparison and hence eliminates the need of additional comparators for acceleration as compared with the existing methods. In addition, a digital self-learning module is also presented, which calculates the uncertainty window required for bound update in the proposed method and thus adjusts to different process corners. To validate these concepts, a 10-bit SAR ADC is designed in 130nm CMOS process with 0.5V power supply voltage. The circuit operates in both conventional and proposed modes. Simulations show that the largest number of conversion cycles is 7, hence resulting in an acceleration of 30% over the conventional scheme, while the average number of cycles is 5.58. Simulation results also demonstrate that the proposed method does not affect accuracy. Both ADC operation modes achieve SNDR (signal-to-noise distortion ratio) of 59dB, corresponding to an ENOB (effective number of bits) of 9.5-bits.

A one-step sneak-path free read scheme for resistive crossbar memory is proposed in this article. During read operation, it configures the crossbar array into a four-terminal resistance network, which is composed of the selected cell and three other resistors corresponding to unselected cells that contribute to the sneak-path. Two sensing voltages with equal potential are applied to three terminals of the network. One is for sensing the resistance of the selected cell; the other is for creating zero-voltage drop across one of the three resistors, which connects the sneak-path to the selected cell. This effectively suppresses the current injected by the sneak-path to the selected cell-sensing loop. This work also proposes a cost-effective data-encoding circuit that guarantees that at least half of the memory cells are in a high-resistance state, which further minimizes sneak-path current. The impact of key design parameters, such as sensing voltage, switch on-resistance, and the ratio of memory cell resistances in different states, as well as nonideal effects are investigated. Equations for estimating the maximum array size to share a single read circuit are derived. The effectiveness of the proposed design has been validated via circuit simulations. Impacts of the word-/bit-line resistance are also analyzed.

Compressive sensing has been demonstrated as an appealing technique in the implementation of low-power sensors. This work studies the feasibility and potential power savings by adaptively adjusting the sampling rates in compressive sensing operations, which is referred to as adaptive compressive sensing in this paper. The results reveal that the sparsity of many biomedical sensor signals varies over time and hence it is possible to perform such adaptive operations. The study also shows that the adaptive operation can lead to significant reduction on sensor node power consumption

Voltage comparators have been widely used in low-power sensor wake-up circuits for extracting digital bits from the envelope of received RF signals. This paper presents an alternative circuit to such comparators. The proposed circuit extracts digital bits by detecting the falling edge of the envelope signal. Since it essentially compares the values of the same signal at different times, it is potentially more robust than the comparator based approach, which compares the peak voltage of the envelope signal with another reference voltage. The design issues for using the proposed edge detection circuit into different wake-up receiver architectures are discussed and simulation results are also presented to demonstrate the performance of the proposed circuit.

We report our results on pulse-forming-line (PFL)-based CMOS pulse generator studies. Through simulations, we clarify the effects of PFL length, switch speed, and switch resistance on the output pulses. We model and analyze CMOS pulse generators with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In a 0.13- μm CMOS process with a 500- μm long PFL, post-layout simulations show that pulses of 10.4-ps width can be obtained. High-voltage and high-power outputs can be generated with other pulsed power circuits, such as Blumlein PFLs with stacked MOSFET switches. Thus, the PFL circuit significantly extends short and high-power pulse generation capabilities of CMOS technologies. A CMOS circuit with a 4-mm-long PFL is implemented in the commercial 0.13- μm technology. Pulses of ~116-ps duration and 205-300-mV amplitude on a 50-Ω load are obtained when the power supply is tuned from 1.2 to 1.6 V. Measurement connection setup is the main reason for the discrepancies among measurements, modeling, and simulation analyses.

Abstract Intrusion Detection Systems (IDSs) rely on pattern matching to detect and thwart a network attack by comparing packets with a database of known attack patterns. The key requirements of trusted intrusion detection are accurate pattern matching, adaptive, and reliable reconfiguration for new patterns. To address these requirements, this paper presents a trusted intrusion detection by utilizing hybrid pattern matching engines: FPGA‐based and multicore‐based pattern matching engine. To achieve synchronization of these two pattern matching engines, methodologies including multi‐threading DFA and clustered state coding have been developed. These hybrid pattern matching engines increases the reliability and trustworthy of intrusion detection systems. Copyright © 2009 John Wiley & Sons, Ltd.

This paper presents a string matching hardware on FPGA for network intrusion detection systems. The proposed architecture, consisting of packet classifiers and strings matching verifiers, achieves superb throughput by using several mechanisms. First, based on incoming packet contents, the packet classifiers can dramatically reduce the number of strings to be matched for each packet and, accordingly, feed the packet to a proper verifier to conduct matching. Second, a novel multi-threading finite state machine (FSM) is proposed, which improves FSM clock frequency and allows multiple packets to be examined by a single FSM simultaneously. Design techniques for high-speed interconnect and interface circuits are also presented. Experimental results are presented to explore the trade-offs between system performance, strings partition granularity and hardware resource cost

This paper presents a novel design of analog window comparator circuit. The comparator can adaptively adjust its error threshold according to the magnitude of input signal levels. In addition, the circuit can be digitally programmed to realize different error threshold adapting schemes. The design is fabricated using a0.18μmCMOS technology. Testing results of the fabricated chip are also presented.

This paper discusses the challenge of designing window comparators for analog online testing applications. A programmable window comparator with adaptive error threshold is presented. Experimental results demonstrate that improved fault detection capability is achieved by using the proposed design. Measurement results of the fabricated comparator circuit are also presented.

This paper presents techniques to model the impact of parametric faults on the performance of programmable capacitor arrays (PCAs). Closed-form equations are derived for estimating ranges of parametric faults that can be detected by integrator-based PCA testing circuits. Methods to improve PCA testing efficiency are discussed and experimental results are reported.

This work presents an efficient methodology to on-line test field programmable analog array (FPAA) circuits. It proposes to partition the FPAA circuit under test into sub circuits. Each sub circuit is tested by replicating the sub circuit with programmable resources on FPAAs, and comparing the outputs of the original partitioned sub circuit and its replication. The advantages of this approach includes: low implementation cost, enhanced testability, and flexible testing schedules. This work also presents circuit techniques to address stability problems which are often encountered in the proposed on-line testing approach. In addition, the impact of performing circuit partition on testability is investigated in this work. It shows that testability is generally improved in partitioned circuits. Finally, experimental results are presented to demonstrate the feasibility and effectiveness of the proposed techniques.

This article presents methods to translate a behavioral-level analog description into a Field Programmable Analog Array (FPAA) implementation. The methods consist of several steps that are referred to as function decomposition, macrocell synthesis, placement and routing, and postplacement simulation. The focus of this article is on the first three steps. The function decomposition step deals with decomposing a high-order system function into a set of lower-order functions. We present an efficient procedure for searching for an optimal solution. This procedure is based on first formally demonstrating the equivalence of two previously used optimization criteria. The objective of the macrocell synthesis step is to generate a hardware realization. A modified signal flow graph is introduced to represent FPAA circuits and graph transformations are used to identify the realizations that comply with the FPAA hardware constraints. The modified signal flow graph also allows scaling of capacitor values due to the limited set of allowable values in an FPAA. For the placement and routing step, an efficient method to estimate the circuit performance degradation due to parasitic effects is given. Using performance degradation as the cost function, an algorithm for finding an optimal FPAA placement and routing configuration is given. The efficacy of the methods developed is demonstrated by direct measurements on a set of filters.