With the increasing network speed over Ethernet, the servers and communication systems has become burdened with the large amount of TCP/IP processing required. The main reason for the CPU bottleneck is the TCP/IP stack being processing at a rate less than network speed. In recent years, TCP/IP offload engine (TOE) is emerging as an attractive solution, which can reduce the host CPU overhead and improve network performance at the same time. The objective of this paper is therefore to design and implement a TOE offload system which attempts to offload the processing of TCP/IP protocols onto our designed host bus adapter. We have also implemented our TOE acceleration hardware block and associated TCP firmware to accomplish this goal. The experimental results show that our offload system can provide better TCP/IP transmission rate up to 296 Mbps as receiver and 239 Mbps as sender compared with embedded OS based solutions.

We present the design of an iSCSI hardware accelerator for the initiator subsystem of a host bus adapter (iSCSI HBA). By analyzing the UNH-iSCSI open source code, first we evaluate the software performance and present a general methodology that transforms the software C code into the hardware HDL implementation. For the hardware module, the datapath design maximizes the concurrent accesses achievable within a clock cycle by using a dual-port descriptor memory. The synthesizable iSCSI hardware accelerator achieves 100 MHz speed and costs about 85K gates in the 0.18u technology. The design is able to meet the requirement of 1Gbps network when the average iSCSI PDU size is greater than 125 bytes

This paper presents the design of a speech recognition and compression chip for portable memopad devices, especially suitable for use by the visually impaired. The proposed chip design is based on several cores of which they can be regarded as intellectual property (IP) cores to be used for a variety of speech-related application systems. A cepstrum extraction core and a dynamic warping core are designed for mapping the speech recognition algorithms. In the cepstrum extraction core, a novel architecture computes the autocorrelation between the overlapping frames using two pairs of shift registers and an intelligent accumulation procedure. The architecture of the dynamic time warping core uses only a single processing element, and is based on our extensive study of the relationship among the nodes in the dynamic time warping lattice. Bit rate is the key factor affecting the memory size for speech compression; therefore, a very low bit-rate speech coder is used. The speech coder exploits a line-spectrum-based interpolation method, which yields fine quality synthesized speech despite the low 1.6 kbps bit rate. The 1.6 kbps vocoder core is cost-effective, and it integrates both encoder and decoder algorithms. The proposed design has been tested via hardware simulations on Xilinx Virtex series FPGAs and a semi-custom chip fabricated by 0.35 /spl mu/m CMOS single-poly-four-metal technology on a die size approximately 4.46/spl times/4.46 mm/sup 2/.

In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch detection algorithm avoids the heavy computational load introduced by the traditional normalized autocorrelation method. The memory storing triangular function value is no longer needed after adopting the new LSP decoding process. The chip is designed with area effective feature and is suitable for stand alone application.