Khosro Rouz

dblp:71/4183 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.112007
Two-Stage Newton-Raphson Method for Transistor-Level Simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › circuit simulation › analog circuit simulation
SPICE simulation
0.112007
Two-Stage Newton-Raphson Method for Transistor-Level Simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › circuit simulation › device and circuit simulation
transistor-level simulation
0.112007
Two-Stage Newton-Raphson Method for Transistor-Level Simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007

Methods — techniques the papers use, named apart from their topics

newton-raphson method · 0.1multigrid · 0.1
YearPublicationVenuePosition
2007 Two-Stage Newton-Raphson Method for Transistor-Level Simulation
abstract
In this paper, we introduce an efficient transistorlevel simulation tool with SPICE-accuracy for deepsubmicrometer very large-scale integration circuits with strong-coupling effects. The new approach uses multigrid for huge networks of power/ground, clock, and interconnect with strong coupling. Mutual inductance can be incorporated without error-prone matrix sparsification approximations or expensive matrix inversion. Transistor devices are integrated using a novel two-stage Newton–Raphson method to dynamically model the linear network and nonlinear devices boundary. Orders-ofmagnitude speedup over Berkeley SPICE3 is observed for sets of real deep-submicrometer design circuits.
Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2005 Efficient transient simulation for transistor-level analysis
abstract
In this paper, we introduce an efficient transistor level simulation tool with SPICE-accuracy for deep-submicron(DSM) VLSI circuits with strong coupling effects. The new approach uses multigrid for large networks of power/ground, clock and signal interconnect. Transistor devices are integrated using a novel two-stage Newton-Raphson method to dynamically model the linear network and nonlinear devices interface. Orders of magnitude speedup over Berkeley SPICE3 is observed for sets of DSM design circuits.
Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh
ASP-DAC2