Xiaopeng Li, Yuanjin Zheng, Wanyu Wang, Wenlin Zhang, Pengyue Jia, Yingyi Zhang, Haiying He, Mengyang Ma, Yiqi Wang, Maolin Wang, Xuetao Wei, Xiangyu Zhao. Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers). 2026.

The multiscroll chaotic system, with its complex phase space topology, offers broad applicability in real-time path planning for the Internet of Things (IoT). In this work, it is found that the combination of attractor doubling can help to reconstruct or even strengthen the bidirectional bonding strap, and thus cooperate with the dynamics editing for building and reshaping any desired multiscroll topological structure. From this routine, 2-D or 3-D controlled multiscroll attractors can be produced, in which the technology of attractor doubling and dynamics editing can be combined in a flexible strategy, and thus the multiscroll attractors present richer embedded forms. Additionally, the proposed concepts of convergence fields and switching regions provide a new analytical perspective for understanding multiscroll structures. FPGA-based hardware experiments successfully verify the feasibility of implementing such systems on embedded platforms. Test results indicate that integrating the Pelican Optimization Algorithm (POA) with the multiscroll system yields an average performance improvement of approximately 5%.

This paper presents a highly dense SRAM-based computation-in-memory (CIM) architecture designed for area-efficient AI acceleration. The proposed architecture leverages charge redistribution in a capacitor-based CIM design to enhance linearity, effectively mitigating the impact of variable parasitic capacitance inherent in FETs. To address the dynamic range mismatch between the CIM array and the ADC, a dynamic range calibration scheme is introduced. Recognizing the significant area overhead of ADCs in CIM, this work also proposes an area-efficient SR-latch-based cap-DAC driver. Furthermore, this work compares and analyzes various ADC comparator reference types, ultimately proposing individual reference columns with global drivers to achieve both ADC symmetry and improved area/power efficiency. Fabricated using a 65nm LP process, the prototype occupies a core area of 0.265 mm2, comprising a 108kb ($432\times 256$) SRAM-CIM array and 256 column-by-column ADCs with peripherals. This design achieves a weight density of 415.4 kb/mm2. By employing column-by-column ADCs, which avoid the throughput limitations of ADC sharing, the prototype achieves an energy efficiency of 95.4 TOPS/W and a throughput of 813.6 GOPS. The resulting area and energy-efficient architecture achieves a SWaP (space, watt, and performance) figure-of-merit of 39.63 TOPS/W$\times $Mb/mm2.

This article presents a cryogenic fractional-N 4–5.9-GHz cascaded phase-locked loop (PLL) operating down to 4 K for a transmon control system. The main PLL stage employs a supply-boost constant charging current sampling phase detector (SBCC-SPD) to achieve ultralow rms jitter and fractional spur from 300 to 4 K. The first-stage PLL operates in integer-N mode employing an inverter-based sampling PD and a Class-F voltage-controlled oscillator (VCO) to achieve low output phase noise, with a frequency-tuning range of 11.8–15.9 GHz. The second-stage PLL operates in fractional-N mode using double-multimodule divider (MMD) with shared delta-sigma-modulator (DSM) architecture. It incorporates an SBCC-SPD and Class-B VCO, with a frequency-tuning range of 4–5.9 GHz for transmon control application. The reference signal of SBCC-SPD is from the divided signal of the first-stage PLL, which is modulated by the same DSM used in the feedback path of the second-stage PLL to compensate for the quantization error. Fabricated in a 28-nm Bulk CMOS process, the PLL achieves an rms jitter of 58.8 fs at 300 K and 36.9 fs at 4 K, with a fractional spur of −71.8 dBc at 300 K and −69.1 dBc at 4 K. The chip consumes a power consumption of 24.8 mW at 300 K and 14.2 mW at 4K corresponding to a figure of merit (FOM) of −257.1 dB. This chip occupies an area of 0.344 mm2.

Spectrum mapping (SM) visualizes spectrum information across a geographical area, constructing radio environment maps (REMs), which serve as a foundation for spectrum monitoring, management, and security. Most existing SM schemes rely on spatially distributed sensors or vehicle-mounted equipment, and assume prior environmental knowledge, limiting their applicability in dynamic or unknown 3D environments. In this paper, we propose a Bayesian learning-based three-dimensional (3D) SM framework that enables accurate REM construction through adaptive UAV sampling in complex and unknown environments. First, a mutual-information-driven UAV path planner is designed by integrating an enhanced sampling-based optimization scheme, enabling efficient data collection according to the maximum mutual information criterion and recent sensing data. Second, a semi-deterministic channel dictionary, refined with sampled field data, is established to model the correlation between observed spectrum values and environmental features. Based on this dictionary, a Bayesian learning-based recovery algorithm reconstructs the spectrum distribution at unsampled positions, producing the corresponding 3D REM. Experimental results on open simulated and measured datasets demonstrate that the proposed framework reduces the mean absolute error by over 60% compared with CS-based methods and by 35% with data-driven interpolation. It also improves sampling efficiency by up to 70% for a given recovery accuracy, highlighting the effectiveness in unknown 3D environments.

The growing demand for high-performance components in wireless communication and automotive systems, especially for radar applications, has driven the need for dual-band power amplifiers (PAs) operating at 60GHz and 77GHz. These frequency bands are particularly beneficial for automotive radar systems, integral to Advanced Driver Assistance Systems (ADAS) and autonomous driving technologies, as they offer enhanced resolution, reduced interference, and faster data transmission rates. This paper presents the design and development of a dual-band PA based on a novel coupled-line dual-frequency matching structure. The PA’s innovative input and output matching networks utilize a unique coupler design to achieve simultaneous impedance matching at both 60GHz and 77GHz. Through comprehensive simulation, optimal matching impedances for both frequencies were identified, enabling the PA to achieve an output power of 12 dBm at 60GHz and 10 dBm at 77GHz, with power-added efficiencies of 24.4% and 13.85%, respectively. The design also incorporates a two-stage power amplifier configuration that ensures high efficiency and gain across the dual bands. Experimental validation was performed using a small-signal test system, demonstrating excellent performance, with a peak power gain of 12.4 dB at 60GHz and 9.8 dB at 77GHz. This dual-band PA design is particularly well-suited for integration into automotive radar systems, thanks to its compact size, high power efficiency, and ability to support wideband matching. Furthermore, this work presents a highly efficient, wideband solution for next-generation automotive radar and communication systems operating in the millimeter-wave frequency range.

Recent advancements have marked significant progress in photoacoustic imaging as an effective method for acquiring deep bio-tissue visuals in modern medical clinical therapy and the efficacy of U-Net and its variants has been established for imaging quality enhancement in this field. Unlike common computer vision datasets such as ImageNet [1] and PASCAL VOC [2], biomedical images exhibit highly structured patterns, low spatial resolution, and single-channel modality, as shown in Fig. 1. Additionally, the U-Net parameters trained for medical super-resolution tasks demonstrate a high sparsity ratio, making them suitable for implementation on edge-computing platforms. Therefore, developing an energy-efficient photoacoustic imaging setup in this area is a natural progression. However, this development is constrained by the current neural network architectures, which are built around a U-Net backbone. The multi-stage feature extractor, skip connection integration across different blocks, and the encoder-decoder backbone design pose significant challenges to cutting-edge computational hardware platforms. In this study, a scalable, sparsity-supported neural network accelerator architecture for bio-tissue imaging quality enhancement is proposed to meet the stringent requirements of latency and energy efficiency, as depicted in Fig. 2. This architecture achieves desired performance improvements by exploring the sparsity possibilities in neural network during the training process and implementing an end-to-end pixel-first hardware design to minimize data movement and support sparsity computation. Compared with the state-of-the-art related works, this optimized architecture has achieved minimum on-chip storage overhead and the fastest frame for the application of photoacoustic imaging quality enhancement. The scalable architecture has also been implemented on a Xilinx XCZU9EG FPGA and attains a performance of PSNR@ 24 dB and a frame rate of 164 fps at a working frequency of 250 MHz.

This paper proposes a compact sub-THz frequency conversion module for D-band transceivers, fabricated using a 28-nm CMOS process. The module integrates an injection-locked frequency multiplier (ILFM) for Tx signal frequency up-conversion and an active Gilbert double-balanced mixer for Rx signal frequency down-conversion. The system was tested on a probe station. Utilizing a tunable coupling-coil technique and optimized inductance, the ILFM achieves a locking range of 105.2-125.5 GHz with an output power of -4.5 dBm. The Gilbert mixer demonstrates a conversion loss of -6.5 dB across the same range with an LO power of -4.2 dBm. The active region of ILFM and mixer chips occupy areas of 0.31 mm2and 0.51 mm2, respectively.

This paper proposes a 1.5 GS/s 9-bit two-stage pipelined SAR analog-to-digital converter (ADC) in 28 nm CMOS. Simultaneously with amplification, the inter-stage residue is converted to time-domain (TD) and quantized by a TDC. This results in significant resolution improvement of the second stage under the speed of 1.5 GS/s. A double-edge quantized TDC with improved time resolution is proposed for higher conversion speed in the time domain and less power consumption. Moreover, a cascode switching inverter-based open-loop amplifier is proposed featuring low gain error, fast settling, and low power. With a sampling speed of 1.5 GS/s, the simulation results show that the ADC achieves 55 dB SNDR and 66.7 dB SFDR at the Nyquist frequency and 1-Vppinput swing, while the power consumption is 6.86 mW, yielding a Walden FoM of 10.2 fJ/con-step.

Partial discharge (PD) detection is critical for diagnosing and maintaining insulation systems of high-voltage equipment. In this article, a novel broadband three-directional (3-D) omnidirectional magnetic induction-based sensor module is proposed for noncontacting PD detection of high-voltage equipment in the industrial Internet of Things (IIoT) application. The equivalent circuit models of a bandpass filter and planar spiral coil are comparatively investigated. Both broadband and filtering performance are realized by combining multiple spiral coils associated with the lumped capacitors. Moreover, five coils are wrapped around the dielectric cube to construct a 3-D omnidirectional sensor. Benefiting from the subcoil interactions, the magnetic field vector is redistributed to produce a transverse component that can detect the fields parallel to the coil’s plane, thus contributing to omnidirectional sensing performance. To verify the proposed measurement technique, an IIoT-based real-time monitoring system prototype is manufactured, and the designed sensor is fabricated by using 3-D printing technology. The experiments show that the designed sensor module can achieve an ultrawide impedance bandwidth ranging from 4 to 70 MHz (|$S_{11} {\unicode {0x007C}}$¡ −10 dB) while the out-of-band interference can be suppressed. Besides, the proposed system has been demonstrated for 3-D omnidirectional real-time monitoring and intelligent analysis for PD events, showcasing its significant potential in IIOT applications.

Histogram of Oriented Gradients (HOG) and linear Support Vector Machine (SVM) have been widely used for pedestrian detection in applications like video surveillance, automatic driving, and intelligent robots. However, in Internet of Things (IoT) applications relying on intelligent edge devices, it is a big challenge to design a high frame-rate multi-scale pedestrian detector without sacrificing precision under strictly resource-limited and energy-constrained conditions. This paper proposes a HOG-SVM-based pedestrian detector with a novel multi-scale image scheduling method based parallel-pipelined multi-detector architecture to maintain a high frame rate with small hardware overhead, and an optimized inter-module pipeline design to minimize pipeline cycles and on-chip buffer costs. Besides, a fine-grained block-score Multiply-Accumulate (MAC) segmentation and mapping method is proposed for the SVM-classifier MAC array to reduce resource overhead while maintaining the same throughput. FPGA validation shows that as compared to the state-of-the-art design with 12 multi-scale detectors, our proposed design achieves a frame rate of 288 fps using only 2 parallel detectors, which reduces LUT, FF, BRAM, and Digital Signal Processor (DSP) usage by 68.9%, 76.1%, 63.3%, and 94.4%, respectively, while improving energy efficiency by 48.6%. ASIC implementation further improves the energy efficiency by 97% and at the same time increases the frame rate to 400 fps at 200 MHz.

Accurate partial discharge (PD) detection and insulation diagnosis are essential for ensuring the operational safety of high-voltage (HV) power equipment, while wideband high sensitivity PD detection is extremely imperative since most of the PD events reflecting potential insulation defects have low strength (<1 pC) with wideband features. However, conventional wideband detection methods such as high-frequency (HF) antennas often suffer from the trade-off between low sensitivity, increased noise and the bandwidth requirements due to their low-Q features in the wideband sensing, and the vulnerability to in-band narrowband interference, especially in complex industrial environments. To address these challenges, this paper proposes a novel high sensitivity super-wideband PD detection system for Industrial Internet of Things (IIoT) applications integrating a reconfigurable high-frequency antenna sensor (RHAS), a bandwidth-reconfigurable low-noise amplifier (BRLNA), and a sub-band synthesis algorithm with built-in narrowband interference rejection (NIR) function. The RHAS captures weak PD signals across 48 high-Q sub-bands, which are individually amplified and digitally synthesized to reconstruct the wideband signal with enhanced sensitivity. The proposed system enables remote, clamp-free PD detection with strong NIR capability near grounded conductors, significantly outperforming the traditional sensors such as High-Frequency Current Transformers (HFCTs). Experimental results demonstrate a detection bandwidth from 1.4 MHz to 98.2 MHz (194.38% relative bandwidth) and a minimum detectable PD level of 0.3 pC. Compared with HFCT based systems, the proposed method achieves a 0.4–4.2 dB improvement in PD signal-to-noise ratio (SNR) and a 6.1–8.4 dB increase in total system gain. These results validate the effectiveness and robustness of the proposed approach for high-sensitivity wideband PD monitoring.

The Hopfield neural network with unidirectional fixed resistance weights has been shown to exhibit limited complex dynamical behaviors due to its relatively simple architecture. To address this limitation, this paper proposes a new tri-memristor hyperchaotic ring neural network (THRNN). The THRNN facilitates the generation of hidden chaos and demonstrates homogeneous/heterogeneous multistability. Homogeneous coexisting attractors, when tightly connected across barriers, exhibit significant self-growth behavior over time. The number of growth directions can be freely regulated, and the multidirectional initial offset boosting characteristics of these growing attractors can also be readily observed. Furthermore, abundant hidden firing patterns are well-tuned by the coupling parameters of the memristors, resulting in chaotic bursting firing, periodic bursting firing, chaotic spiking firing, and periodic spiking firing. Particularly, a more complicated hidden hyperchaotic firing pattern is also discovered and captured. Moreover, an STM32H7 digital circuit is built to verify the findings presented in this paper. Finally, a hardware image blocking encryption system based on FPGA and the THRNN is proposed. This encryption system constructs a framework based on the hyperchaotic firing attractors and homogeneous multistability attractors. It realizes dynamic key update through block encryption strategy, and completes key scrambling by combining Cat mapping and sequence sorting, which significantly enhances encryption security. Relying on FPGA hardware implementation, its parallel processing capability greatly improves encryption efficiency, and the hardware deployment feature enhances the system’s stability and practicality, providing an efficient solution for high-security image encryption.

The static architecture of artificial neural networks has fixed synaptic weights, whose connections do not change according to new information or learning experience. In contrast, the capacity of synaptic weight empowers biological neural networks to learn and adapt to diverse tasks, resulting in various dynamical behaviors. In this paper, a novel memristor model is designed into the Hopfield neural network for generating any desired number of multi-scroll attractors. Offset booster provides a channel for distance regulation and number control of coexisting attractors. Independent offset boosters determine the coexisting patterns including the types of one-scroll attractor, two-scroll attractor, four-scroll attractor, and other mixed types. In addition, the digital circuit platform of CH32V307 is applied to verify numerical simulations. Finally, the chaotic data generated in the memristive Hopfield neural network is introduced into the northern goshawk optimization (MHNN-NGO), by which the full network optimization is achieved.

This work presents an algorithm hardware co-design implementing a digital neuronal population dynamics simulator intended for the trajectory error correction task within a simultaneous localization and mapping workflow. A custom discretized procedural algorithm approximating a neuronal population dynamics-based inference operation is developed for mapping onto an ultra-lightweight digital macro featuring massively parallel in-situ processing techniques. Fabricated using a 40nm technology, the test chip features a$22\times 22$neuron array with 0.1358mm2 core area and provides a 12-bit computing precision. A time-multiplexed processing element design prevents the use of excessive silicon area. Accomplished via extensive data reuse through massively parallel processing-in-memory architecture attached to a custom I/O interface, a single inference operation is completed within 3277 clock cycles, providing 200 inferences per second operating at a low frequency of 0.667Mhz with a 0.5V core supply and consuming sub-10-$\mu $W power.

This work proposes the Poisson equation formulation of the Retinex model for image enhancements using a low-power graph hardware accelerator performing finite difference updates on a lattice graph processing element (PE) array. By encapsulating the underlying algorithm in a graph hardware structure, a highly localized dataflow that takes advantage of the physical placement of the PEs is enabled to minimize data movement and maximize data reuse. The on-chip dataflow that achieves data sharing, and reuse among neighboring PEs during massively parallel updates is generated in each PE driven by two external control signals. Using a custom accumulator design intended for bit-serial computing, this work enables precision on demand and extensive on-chip data reuse with minimal area overhead, accommodating a non-overlap image mapping scheme in which a$20\times 20$image tile can be processed without external memory access at a time. With increasing user-configurable update count, image noise and shadow can be progressively removed with the inevitable loss of image details. Fabricated using a 65nm technology, the test chip occupies 0.2955mm2 core area and consumes 2.191mW operating at 1V, 25.6MHz, and a reconfigurable 10- or 14-bit precision.

In this work, a solid-state direct time-of-flight (dToF) and adaptive beam-steering Light Detection and Ranging (LiDAR) system is proposed for machine learning (ML) based object detection. To leverage the capabilities of software and hardware, a co-optimization design from a neural network based algorithm to the architecture of transmitter, receiver and optical components is realized. Firstly, an object detection neural network is proposed for the depth-only input algorithm, which indicates the Region of Interest (ROI) in the illuminating field and gives hints of opened scan channels in the next two frames to decrease the total cost of the laser driver and sensor array. Next, the proposed network utilizes the Cross-Stage-Patrial (CSP) block to replace the residual structure in the backbone to achieve a lightweight performance and is implemented on the NVIDIA-Jetson to verify the system-level adaptive beam steering feature. To realize the smart working mode, a customized multi-channel and addressable TX is designed for adaptive and optical control to save power consumption and extend the ranging distance. At the same time, a 128×80 resolution RX which consists of Single-Photon Avalanche Diodes (SPADs) and column-wise Time-to-Digital Converter (TDC) is incorporated to capture the returned photons for combining sub-regions into an entire depth map. Next, to customize the specific scanning mechanism, for the optical setup, a cylindrical lens array is designed to reshape the laser beam, which matches the pattern of the transmitter to illuminate different targeted objects. Both the laser driver chip and the sensor chip with a 128×80 SPAD array are fabricated in the 180-nm Bipolar-CMOS-DMOS (BCD) process. Finally, the laser driver chip realizes the power of 5 W with an adjustable pulse width of 1.5 ns and the SPAD array integrates the depth accuracy of 5 cm at 15 m. Due to that the neural network realizes an accuracy up to 0.8, a low-power solid-state LiDAR prototype with adaptive beam steering is demonstrated.

Acoustic resolution photoacoustic microscopy (AR-PAM) is a novel medical imaging modality, which can be used for both structural and functional imaging in deep bio-tissue. However, the imaging resolution is degraded and structural details are lost since its dependency on acoustic focusing, which significantly constrains its scope of applications in medical and clinical scenarios. To address the above issue, model-based approaches incorporating traditional analytical prior terms have been employed, making it challenging to capture finer details of anatomical bio-structures. In this paper, we proposed an innovative prior named group sparsity prior for simultaneous reconstruction, which utilizes the non-local structural similarity between patches extracted from internal AR-PAM images. The local image details and resolution are improved while artifacts are also introduced. To mitigate the artifacts introduced by patch-based reconstruction methods, we further integrate an external image dataset as an extra information provider and consolidate the group sparsity prior with a deep denoiser prior. In this way, complementary information can be exploited to improve reconstruction results. Extensive experiments are conducted to enhance the simulated and in vivo AR-PAM imaging results. Specifically, in the simulated images, the mean peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) values have increased from 16.36 dB and 0.46 to 27.62 dB and 0.92, respectively. The in vivo reconstructed results also demonstrate the proposed method achieves superior local and global perceptual qualities, the metrics of signal-to-noise ratio (SNR) and contrast-to-noise ratio (CNR) have significantly increased from 10.59 and 8.61 to 30.83 and 27.54, respectively. Additionally, reconstruction fidelity is validated with the optical resolution photoacoustic microscopy (OR-PAM) data as reference image.

This article presents a single-channel 4-GS/s 8-bit hybrid-domain analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. The proposed 8-bit ADC combines a 3-bit voltage-domain stage with a 6-bit time-domain (TD) backend to take full advantage of the voltage and time domains. A high-speed hybrid-loop residue amplifier (RA) is proposed with a settling time of less than 150 ps, while a non-symmetrical pipeline timing utilizing a 25% duty cycle clock is used to increase the TD quantization time and the settling time margin of the RA. A low-power and small-area gated-ring-oscillator-based TD backend is employed, which operates at 4-GS/s with 6-bit resolution. The prototype hybrid ADC occupies an active area of 0.0114 mm2. Under a 1-V power supply and Nyquist input, the chip achieves a measured ENOB of 6.46 bits at a conversion rate of 4 GS/s, while the power consumption is 10.6 mW and the FoMw is 29.9 fJ/conversion-step.

This paper presents a cryogenic qubit controller for scalable superconducting quantum computing. A phase-selection digital power amplifier (DPA) topology is utilized for the XY-driving pulses generation. With a compact digital extensive architecture, the amplitude modulation and qubit phase rotation can be directly implemented at the phase-selection DPA stage for power reduction. A multi-phase envelope-tracking supply unit is also employed to enhance the power efficiency. The controller was designed and simulated in 28nm bulk CMOS technology. The controller can cover a band of 4-6GHz with an output power of at least -8dBm. The simulated SNR/SFDR is better than 55dB/46dB with a phase rotation error of less than 0.7°. The envelope-tracking supply unit can reduce the DPA power consumption by at least 24% compared to a constant power supply. The total power consumption of the controller is 3.64mW.

In this paper, we demonstrate an energy-efficient real-time object detection and classification system featuring a hybrid event-based frame generation pipeline and a background-removal region proposal algorithm. The event-based frame is generated by aggregating active events within a programmable time interval, generating an event-based binary image (EBBI). This approach enables the utilization of low-complexity algorithms for denoising and object detection. The background-removal region proposal algorithm reduces memory requirements and removes dynamic backgrounds, leading to better detection performance. The proposed system is demonstrated on Zynq-7000 FPGA device with a DAVIS346 sensor. Experimental results show that the proposed system achieves comparable detection accuracy while requiring significantly less computation than existing event-based trackers.

Neuromorphic vision sensors (NVSs) mimic the function of the human visual system, with significant energy-saving potential in IoT-based object detection systems. Unlike conventional sensors, NVSs only generate asynchronous spiking events in response to changes in light intensity. However, the inherent noise generated by NVSs causes a degradation of detection performance. Moreover, an interested object usually occupies only a portion of the entire image frame. Therefore, a real-time, accurate event-based object detection system is needed to identify the region of interest (Rol) and leverage this spatial redundancy to reduce computational load in subsequent recognition modules. In this article, we present an energy-efficient real-time object detection system featuring a hybrid event-based frame generation pipeline and a background-removal region proposal algorithm. The event-based frame is generated by aggregating active events within a programmable time interval, generating an event-based binary image (EBBI). This approach enables the utilization of low-complexity algorithms for denoising and object detection. The background-removal region proposal algorithm reduces memory requirements and removes dynamic backgrounds, leading to better detection performance. The proposed system is demonstrated on Zynq-7000 FPGA device with a DAVIS346 sensor. Experimental results show that the proposed system achieves comparable accuracy while requiring significantly less computation than existing event-based trackers.

This paper focuses on the acquisition and front-end processing of magnetic field information in pulsed magnetic field measurements. Based on the Faraday electromagnetic induction principle, a magnetic field measurement probe was designed, and a front-end processing circuit for pulse magnetic field induction electromotive force was developed for this probe. The sensing probe has a MHz bandwidth response capability, making it well-suited for covering pulse magnetic field applications. The front-end processing circuit is based on analog operational amplifiers and integrates amplification, filtering, and integration circuits. Finally, PSpice simulation software was used to simulate the design. The simulation results, along with experimental results, demonstrate that the magnetic field probe and front-end processing circuit designed in this paper have advantages such as high bandwidth and fast response.

This paper presents a MEMS-based wake-up receiver (WuRX) operating at 825 MHz, with low-power and high-sensitivity. To enhance selectivity and interference rejection, a high-Q MEMS resonator is incorporated, co-designed with the low noise amplifier (LNA) to implement resonant noise matching (RNM), providing passive gain to mitigate the input-referred noise. The receiver is implemented in TSMC 65nm CMOS technology, achieving a sensitivity of −70 dBm at 10-3BER while consuming a mere 2.83 µW of power at a 1 V power supply. Additionally, it attains a SIR of 20 dB at a 2 MHz offset from the center frequency.

Dynamic vision sensors (DVS) have become prevalent in edge vision applications due to their low power and short latency attributes. However, current DVS-based object tracking systems suffer from high power consumption or long processing latency due to high computing intensity of the object detection algorithms. This paper proposes an energy-efficient object detection system through algorithm and hardware co-optimization. We design hardware-efficient denoising and region proposal (RP) algorithms to reduce on-chip memory usage and power consumption. Besides, the processing latency is dramatically reduced thanks to the less computing complexity. The devised algorithm is executed on a heterogeneous platform, with segments particularly sensitive to latency being accelerated via FPGA. An RP processor, supporting both parallel and systolic computing modes, is developed to facilitate the computing-intensive RP generation. Remarkably, the proposed system reduces the on-chip memory by 95.3% in contrast to traditional methods that employ connected component labeling. Moreover, the processing time per frame stands at 92.2 ms, marking a reduction of 82.4% compared to CPU-only operations.

Image restoration through scattering media is a desired yet challenging task in numerous scenarios. Deep learning (DL)-based approaches have seen significant advancements in recent years, achieving impressive performance. However, most existing solutions have been limited to a single network framework to model the inverse scattering process, leading to relatively poor recovery performance. In this paper, we introduce a forward-inverse reinforcement network (FIRNet) to enhance image recovery performance through scattering media, in which two distinct neural networks are designed to model the inverse and forward scattering processes, respectively. A reinforcement training strategy combined with a variation of GAN loss function is implemented to fully exploit the feature extraction ability of these networks, resulting in higher-fidelity image recovery compared to a single network. Experimental results on different datasets showcase the effectiveness and superiority of our proposed two-stage framework. The promising recovery results indicate that FIRNet could pave the way for new opportunities to enhance image restoration performance in related fields.

The timely detection of partial discharge (PD) of high-voltage (HV) power equipment is crucial to mitigate serious consequences such as the degradation of insulation and equipment failure. The ultra-high frequency (UHF) detection method stands out for its efficacy in this regard. In this study, a novel UHF antenna sensor is proposed for PD detection. The antenna's offset structure enables it to detect PD events near a conducting ground wire without being clamped to the wire like the typical high-frequency current transformer (HFCT). Meanwhile, its equivalent circuit is modeled as a ladder-structure band-pass filter (within the consideration of mutual inductances) to realize its wideband properties. Fabricated on a substrate and integrated with a low-noise amplifier, the antenna sensor exhibits a broad impedance bandwidth between 1 MHz and 108 MHz, as demonstrated through measurements in an anechoic chamber. In-lab and on-site systematic experiments affirm the efficiency of the proposed antenna sensor in PD detection. Notably, the Phase-Resolved Partial Discharge (PRPD) pattern is distinctly observable at the backend through Internet connectivity, further confirming the overall monitoring capabilities.

Anomaly Detection System (ADS) is an essential part of a modern gateway Electronic Control Unit (ECU) to detect abnormal behaviors and attacks in vehicles. Among the existing attacks, "one-time" attack is the most challenging to be detected, together with the strict gateway ECU constraints of both microsecond or even nanosecond level real-time budget and limited footprint of code. To address the challenges, we propose to use the self-information theory to generate values for training and testing models, aiming to achieve real-time detection performance for the "one-time" attack that has not been well studied in the past. Second, the generation of self-information is based on logarithm calculation, which leads to the smallest footprint to reduce the cost in Gateway. Finally, our proposed method uses an unsupervised model without the need of training data for anomalies or attacks. We have compared different machine learning methods ranging from typical machine learning models to deep learning models, e.g., Hidden Markov Model (HMM), Support Vector Data Description (SVDD), and Long Short Term Memory (LSTM). Experimental results show that our proposed method achieves 8.7 times lower False Positive Rate (FPR), 1.77 times faster testing time, and 4.88 times smaller footprint.

This work presents an algorithm hardware co-design implementing a digital neuronal population dynamics simulator intended for a component within the back-end of simultaneous localization and mapping. A custom discretized procedural algorithm including injection, finite difference update, activation, and inhibition to approximate neuronal population dynamics is developed for digital implementation. Fabricated using a 40nm technology, the test chip features a scalable neuron 22 × 22 array with 0.1358mm2core area and provides a 12-bit computing precision. A time-multiplexed processing element design prevents the use of excessive silicon area. Accomplished via extensive data reuse through massively parallel processing-in-memory architecture attached to a custom I/O interface, a single inference operation is completed within 3277 clock cycles, providing 200 inferences per second operating at a low frequency of 0.667Mhz with a 0.5V core supply and consuming 2.793µW of power.

In vehicular-to-infrastructure (V2I) applications, as we adopt higher frequencies and antenna array processing for faster data rates, beamforming is a critical enabling technology to preserve high-quality communication links between mobile users and the base station. Traditional beamforming requires overhead in establishing the directional link, compounded by short coherence time of mobile users, which necessitates frequent re-calibration. Recent works consider more efficient strategies by leveraging context information, with position-aware approaches showing promise. Nonetheless, uncertainties in even the most advanced localization and odometry methods can lead to com-pounded errors in position estimation for downstream tasks such as beam alignment and tracking. Our work addresses these challenges by factoring in the uncertainties inherent in practical odometry systems. We propose a beamforming optimization that accounts for this uncertainty, complemented by overparameter- ization strategies novel to this non-linear problem of interest. Our simulation results demonstrate the feasibility of maintaining robust communication links in representative scenarios by lever-aging localization and odometry information, despite challenges posed by a mobile platform's imprecise position estimates.

An innovative artificial magnetic conductor (AMC)-backed quad-band antenna is proposed with gain enhancement, high out-of-band (OoB) rejection, forward radiation improvement, and backward radiation reduction for intelligent Internet of Vehicle (IIoV)-based sensing and communication. It includes a quad-band microstrip radiator and a tetracyclic nested AMC as a reflector. The radiator has a radiating pattern of slotted octagonal patch connected to a rectangular resonant loop, and a meshed defected ground structure (MDGS). The mechanism of resonant frequency generation is derived and analyzed. Then, an AMC reflector with four zero-phases in the reflection coefficient is designed and its equivalent circuit model is established. The AMC unit cell consists of four nested rings and two lumped capacitors. It generates four in-phase reflection bands, which are coincident with the four frequency bands of the radiator. The quad-band antenna gains are enhanced while its profile maintains low due to the in-phase reflection characteristics of the multi-band AMC reflector. To verify the design concept, a prototype with a total size of 95 mm × 101 mm × 21.2 mm is fabricated and measured. The measured 10-dB impedance bandwidths are 2.19-2.54 (14.8%), 3.06-5.25 (52.7%), 6.43-6.96 (7.9%), and 7.71-8.29 (7.3%) GHz, respectively. High OoB rejections between each band reduce electromagnetic interference to feed into radiofrequency circuits. The measured gains and radiation efficiencies range from 3.6 to 8 dBi and from 57.8% to 92%, respectively.

A wearable dual-band and dual-circularly polarized (DBDCP) antenna using a dodecagonal truncate pyramid-shaped artificial magnetic conductor (AMC) reflector for gain enhancement is proposed in this paper. Firstly, a compact deformed quadruple inverted-F antenna (QIFA) with meander-line-shaped radiation patches has been developed as the radiator. Then, to make this QIFA generate different circular polarization (CP) radiation characteristics in two frequency bands, two feeding networks are adopted for realizing lefthand and righthand CP properties simultaneously. Lastly, a novel AMC reflector is employed to improve antenna performance. The presented DBDCP antenna was fabricated to realize lefthand CP (LHCP) in the frequency band of 3.5-4.0 GHz (13.3%) and righthand CP (RHCP) in 5.4-5.9 GHz (8.8%). Due to installation of the AMC reflector, the gains of the antenna are enhanced by about 3-5.3 dB in the lower CP band. The achieved peak gains are about 11.9 dBic and 10.5 dBic at 3.5 GHz (LHCP) and 5.8 GHz (RHCP), respectively. Meanwhile, the antenna’s specific absorption rate (SAR) has been greatly reduced, which meets well the IEEE wearable device standards. It is found that the proposed DBDCP antenna is a promising candidate for the applications of 5G, industrial scientific medical (ISM), WLAN (5.8-GHz), and WiMAX (3.5-GHz) systems in industrial IoT scenarios.

Developing intelligent methods for partial discharge (PD) diagnosis, capable of handling various types of insulation defects in switchgear, has garnered significant attention in recent years. Certain PD signals exhibit similar characteristics, often leading to their confusion with noisy signals during data acquisition. To mitigate noise interference and enhance the precision of PD recognition, this article introduces a novel framework for separating PD signals from noise and acquiring discriminative features for identifying different types of PDs. Specifically, the proposed approach incorporates an adaptive frequency sampling strategy to extract effective and efficient features for the separation of PD signals and noise, followed by the clustering of the captured signals. Phase Resolved PD (PRPD) patterns are then generated for each clustered signal group, forming the PRPD pattern database. In order to identify the informative region within the PRPD patterns, we introduce spatial correlation attention and discriminative feature learning modules. These modules aim to reduce intraclass variance and increase interclass differences in the PRPD patterns. To evaluate the effectiveness of the proposed method in separating PD signals from noise and recognizing different PD patterns, we constructed a PD recognition dataset that encompasses noise as well as three types of PDs: 1) corona, 2) internal, and 3) surface. By conducting experiments and comparing the results with state-of-the-art methods, we demonstrate the performance of our method in achieving accurate PD recognition with a notable improvement of 1.9% on the constructed PD dataset.

Railway scene understanding is key to autonomous train operation and important in active train perception. However, most railway scene understanding methods focus on track extraction and ignore other components of railway scenes. Although several semantic segmentation algorithms are used to identify railway scenes, they are computationally expensive and slow with limits applications in railways. To solve these problems, we propose efficient dual-stream fusion network (EDFNet), a lightweight semantic segmentation algorithm, for understanding railway scenes. First, a dual-stream backbone network based on mobile inverted residual blocks is proposed to extract and fuse detailed features and semantic features. Next, a bi-directional feature pyramid pooling module is proposed to obtain multi-scale features and deep semantic features. Finally, a multi-task aggregate loss is designed to learn semantic and boundary information, thus improving the accuracy without increasing the computational complexity. Extensive experimental results demonstrate that EDFNet outperforms the lightweight state-of-the-art algorithms with high accuracy and fast speed on two railway datasets.

The contact-free sensing nature of Wi-Fi has been leveraged to achieve privacy breaches such askeystroke inference(KI). However, the use ofchannel state information(CSI) in existing attacks is highly questionable due to its signal instability and hardness to acquire. Moreover, such Wi-Fi-based attacks are confined to only one victim because Wi-Fi sensing offers insufficient range resolution to physically differentiate multiple victims. To this end, we propose MuKI-Fi to enable, for the first time,multi-personKI, leveragingbeamforming feedback information(BFI), a new feature offered by latest Wi-Fi hardware, transmitted in clear-text by smartphones. BFI's characteristics, clear-text communication and signal stability, make it readily acquirable and usable by any other Wi-Fi devices switching to monitor mode without the need forlow-levelhacking on hardware. Moreover, to improve upon existing KI methods offering very limited generalizability across diversified application scenarios, MuKI-Fi innovates in an adversarial learning scheme to enable its inference generalizable towards unseen scenarios. Finally, we discover that, as a smartphone is in close proximity to a victim, the variations of BFI caused by that victim's keystrokes in suchnear-fieldsubstantially outweigh those caused by other distant victims; this phenomenon naturally allows for multi-person KI. Our extensive evaluations clearly demonstrate that MuKI-Fi can effectively eavesdrop on the keystrokes of multiple subjects, achieving 87.1% accuracy for individual keystrokes and up to 81% top-100 accuracy for stealing passwords from mobile applications(e.g., WeChat) on average.

Among many -winners-take-all ( WTA) models, the dual-neural network (DNN- WTA) model is with significantly less number of connections. However, for analog realization, noise is inevitable and affects the operational correctness of the WTA process. Most existing results focus on the effect of additive noise. This brief studies the effect of time-varying multiplicative input noise. Two scenarios are considered. The first one is the bounded noise case, in which only the noise range is known. Another one is for the general noise distribution case, in which we either know the noise distribution or have noise samples. For each scenario, we first prove the convergence property of the DNN- WTA model under multiplicative input noise and then provide an efficient method to determine whether a noise-affected DNN- WTA network performs the correct WTA process for a given set of inputs. With the two methods, we can efficiently measure the probability of the network performing the correct WTA process. In addition, for the case of the inputs being uniformly distributed, we derive two closed-form expressions, one for each scenario, for estimating the probability of the model having correct operation. Finally, we conduct simulations to verify our theoretical results.

This paper presents a hardware-software co-designed system for real-time online monitoring of Partial Discharge (PD) in the Power Grid without human interaction. PD is a critical indicator of insulation degradation, which can lead to premature failure of components and disrupt reliable electric supply. The proposed system utilizes an SoC-based Edge Computing Unit for long-term monitoring activities. It incorporates a wavelet denoising module, an auto management program, and an AI-based detection model to enable automatic PD alarm generation. The system is tested and iterated in a controlled lab environment, capturing standard PD signals. The AI classification model is trained using manually labeled PRPD pattern datasets. Subsequently, the system is deployed in a real power grid for long-term, real-time PD monitoring. The effectiveness of the proposed system is demonstrated through experimental setups and result analysis. The SoC-based real-time online PD monitoring system offers a proactive approach to safeguarding power equipment by detecting and addressing insulation degradation in the Power Grid.

Partial discharge (PD) is an essential indication of insulation degradation in high-voltage power equipment like gas-insulated switchgears (GIS). However, in certain applications that are exposed to intense external noise, traditional PD detection methods often encounter numerous challenges due to their vulnerability to noise and interference. This paper proposes a low-noise ultra-high frequency (UHF) sensing system for PD detection and classification. In analog front end, the noise performance is optimized using a broadband noise-shaping network (BNSN) integrated with a wideband printed monopole antenna (PMA). In digital back end, the combination of noise cancellation, wavelet time scattering (WTS) based features extraction and a support vector machine (SVM), yields 95% correct classification. Simulation and Comparative experimental results validate superior noise performance, effectiveness and accuracy of this UHF sensing system.

CMOS circuits operating at cryogenic temperature are gaining interest as one of the most promising approaches to efficiently scale up quantum processors in near- and medium future. However, there are major challenges such as (1) strict power dissipation limit at 4K plate due to the limited cooling power of the dilution fridge and (2) significant shifts in CMOS device behavior (i.e. variations, threshold voltage, charge carrier mobility and sub-threshold slope) which are not accurately captured in the standard BSIM models from the foundries. Although there have been extensive works experimentally characterizing and analyzing CMOS transistors at ∼4 K, there is a lack of digital and memory subsystem study. Since on-chip SRAM is one of the most power-consuming and the most vulnerable element in cryogenic SoC, this work analyzes the stability of low-voltage 6T-SRAM at deep cryogenic temperature (i.e 77K and 8K), in comparison with 300K operation. Our DC analysis showed that in general, Write static noise margins of the SRAM cell improves when temperature changes from 300K to 8K, even at low-voltage condition. Regarding the Read static noise margin, our simulation showed that the inverters exhibit pseudo-static hysteresis and interestingly this leads to an improvement of read static noise margin of the cell, similar to what observed in a Schmitt-Trigger SRAM. These results suggest that although CMOS transistors exhibit higher threshold voltage in cryogenic temperature, it is still possible to operate the SRAM at low-voltage for power saving in quantum computing applications.

Due to better efficiency, gain and thermal performance compared to other semiconductor technologies, GaN power amplifiers are very attractive in the present 5G era. Meanwhile, accurate GaN HEMT device modelling is one of the critical steps to design PAs successfully. Therefore, research on high-frequency GaN HEMT device modelling method is of vital importance. This paper first presents a wideband GaN HEMTs model for 5G power amplifiers. A loadpull system available for 10-67 GHz measurement is set up to obtain wideband S parameter and RF performance results. The whole GaN device modelling could be divided into two parts: the small signal modelling and the large signal modelling. Direct optimization method with polynomial fitting is employed to obtain equivalent small signal circuit parameters, which improve the accuracy and efficiency of parameter extraction. Also, artificial neural network (ANN) technique is utilized to build charge and nonlinear current models, which takes the self-heating and trapping effects into consideration in the large signal modelling. The ANN technique could substitute the complex empirical equations as other papers has reported, and thus makes the extracted parameters less and the extraction process more accurate and efficient. At last, the proposed model is implemented and verified in ADS, the error between the measurement and simulation results is less than 5%.

This work implements the Poisson equation formulation of the Retinex model for image enhancements using a graph hardware accelerator performing finite difference updates on a 2D lattice graph PE array. A single clock gating control signal manages the data flow, data sharing, and reuse pattern among neighboring PEs during massively parallel updates. With increasing user-configurable update count, image noise and shadow can be progressively removed with the inevitable loss of image details. Accommodating a non-overlap image mapping scheme in which a$20\times 20$image tile can be processed without external memory access at a time, the proposed accelerator consists of 18$\times 18$regular PEs surrounded by$4\times 20$boundary PEs with reconfigurable data flow and 4 boundary cache registers. Fabricated using a 65nm technology, the test chip occupies 0.2955mm2core area, and consumes 2.191mW operating at 1V, 25.6MHz, and a reconfigurable 10- or 14-bit precision.

In this paper, a fast bearing state detection method based on multi-sensor signal fusion and compression feature extraction is proposed. The best estimation in the random weighted fusion algorithm is adaptively adjusted by the fluctuation factor to realize the high-precision fusion of variable signals and reduce the noise component in the signals. In the compressed sensing framework, a partial Hadamard matrix is selected as the measurement matrix, and the signal reconstruction is abandoned, leading to reduced average sampling rate and less data for signal acquisition, transmission, and extraction of fault features. The proposed method for diagnosis of rolling bearing fault is fast, effective, and accurate, as verified by experimental results.

With the rapid development of the techniques of semiconductors, Internet of Everything (IoE), industry 4.0 and smart power are going to be realized, agile and accurate edge detection on pulse signals becomes essential for supporting versatile sensing applications targeting ubiquitous IoE monitoring. To ensure accurate pulse signal sensing at the edge with low power, a novel silicon-integrated mixer-enabled adaptive sensing platform is proposed. Based on the innovative chip architecture composed of the low-power ring voltage-controlled oscillator (VCO) and current-bleeding mixer on-chip, the wideband pulse signal would be mixed with the sinusoidal LO signal generated by VCO and detected by low-pass filtering and further digital processing. The frequency of the VCO can be configured flexibly by the FPGA to cover different pulse detection scenarios. Moreover, the VGA and the LPF are flexibly configurable to meet the link budget requirements and ensure accurate and adaptable detection covering various scenarios. Based on the systematic theoretical evaluation of the novel flexible sensing chip architecture, target pulse signals can be detected, exploring the capability of the efficient chip-based edge pulse detection system to be deployed for applications such as sustainable partial discharge detection for power electronics monitoring, ultrasound sensing, and so on.

A novel mixed-signal adaptable silicon-based coherent photoacoustic (PA) sensing system-on-chip (SoC) is proposed to detect various kinds of target signals robustly under high noise and strong interferences in compact chip-level, attaining precise in vivo sensing for physiological signs monitoring and enhanced bio-imaging. Based on the configurable coherent PA sensing SoC architecture supported by on-chip Gilbert cell-based multiplier, a digital processing module, and DACs, in-phase (I) and quadrature (Q) templates generated by digital module on-chip are configurable to be with a high correlation coefficient to the target PA signal, attaining detection and reconstruction of target signals in a coherent detection mode. The correlation between the received PA signal and the templates is implemented efficiently, assuring accurate tracking and precise reconstruction on the target PA signals at the chip level. Based on the integrated PA SoC fabricated by the TSMC 65-nm CMOS process, precise in vivo sensing and imaging can be assured at the edge. Further, as PA detection leverages optical and ultrasound sensing, in vivo imaging on in-depth vessels or other tissues can be attained. The mixed-signal PA SoC paves the way for sustainable health monitoring and owns immense potential for early disease diagnostics based on in vivo blood temperature sensing and vessel imaging.

A 12th-order active-RC bandpass filter (BPF) for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed BPF is composed of six cascaded Biquads and each Biquad is configured as a second-order bandpass stage and the switched resistor and capacitor arrays are used in the Biquad to enable the digital control of the passband center frequency and bandwidth. To achieve desired passband and behave with Chebyshev response, the capacitors in the six Biquads are designed with the same values and resistor values are tunable. The filter has been implemented in a 65 nm CMOS technology and achieved low ripple, low noise and low power consumption. Under 8-bit digital programmable, the center frequency is tunable from 0.98 MHz to 4.83 MHz and the bandwidth is tunable from 0.66 MHz to 5 MHz, and it measures a maximum in-band frequency response deviation of <0.6dB while consuming $\leq$12mW at a 1.2 V supply.

Optical resolution photoacoustic microscopy (OR-PAM) imaging method can achieve high lateral resolution $(\lt 5 \mu \mathrm{m})$, while the penetration depth for OR is shallow (up to $1 \sim 2$ mm). In contrast, acoustic resolution photoacoustic microscopy (AR-PAM) imaging only has limited lateral resolution $(\gt 50 \mu \mathrm{m})$ but with deeper penetration depth up to several millimeters (3-10 mm). Enlighted by the recent progress in the field of machine learning, we proposed to enhance AR-PAM to OR-PAM while maintaining its high penetration depth merit with deep neural network, where a novel network structure named MultiResU-Net is employed. By training the network with OR images obtained with real setup and AR images simulated with physical model, the network is able to enhance the image quality of simulated AR image a huge extent that is similar to OR image. More importantly, the trained model is applied to real AR imaging system for both phantom and in vivo image enhancement. When compared with corresponding ground truth OR images, it can be fully substantiated that our proposed method realized the AR to OR target in real photoacoustic microscopy imaging system.

Visual feature extraction is a key technology of computer vision for intelligent video processing. Efficient feature extraction is a fundamental problem in computer vision applications. Scale-Invariant Feature Transform (SIFT) is one of the most popular feature extraction algorithms because SIFT features are invariant to image scale and rotation and robust to changes in illumination and noise. However, SIFT is a computationally-intensive and power-hungry algorithm, which needs to be accelerated by efficient hardware design to achieve both high-speed feature extraction and high energy efficiency for many high frame-rate video applications at Artificial-intelligent Internet of Things edges. In this work, an energy-efficient SIFT based feature extraction accelerator is proposed. In the Gaussian pyramid and Differences of Gaussian (DoG) pyramid construction process, three design methods are proposed to reduce power consumption and improve information fidelity: a fast and slow dual clock domain design method with a reconfigurable design strategy is proposed to reduce the computation resources; a partial sum reuse design method is proposed to further reduce the computation resources and the amount of computation; a dynamic padding design method is proposed to solve the problem of information loss at image edges and corners after convolution operation. In the keypoint descriptor generation process, an optimized algorithm using circular region and polar coordinates is proposed to parallelize the main orientation assignment and descriptor generation to achieve high-speed processing, while maintaining a comparable matching accuracy with the state-of-the-art designs. The experiment results show that the proposed SIFT hardware accelerator is able to extract features by up to 162 frames per second ($640\times 480$pixels) under 100 MHz, with the power consumption of 364.26 mW and energy efficiency of 2.25 mJ/frame based on 180 nm technology, which is suitable for many high frame-rate AIoT applications including autonomous driving cars and unmanned aerial vehicles.

Acoustic resolution photoacoustic micros- copy (AR-PAM) can achieve deeper imaging depth in biological tissue, with the sacrifice of imaging resolution compared with optical resolution photoacoustic microscopy (OR-PAM). Here we aim to enhance the AR-PAM image quality towards OR-PAM image, which specifically includes the enhancement of imaging resolution, restoration of micro-vasculatures, and reduction of artifacts. To address this issue, a network (MultiResU-Net) is first trained as generative model with simulated AR-OR image pairs, which are synthesized with physical transducer model. Moderate enhancement results can already be obtained when applying this model to in vivo AR imaging data. Nevertheless, the perceptual quality is unsatisfactory due to domain shift. Further, domain transfer learning technique under generative adversarial network (GAN) framework is proposed to drive the enhanced image's manifold towards that of real OR image. In this way, perceptually convincing AR to OR enhancement result is obtained, which can also be supported by quantitative analysis. Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index (SSIM) values are significantly increased from 14.74 dB to 19.01 dB and from 0.1974 to 0.2937, respectively, validating the improvement of reconstruction correctness and overall perceptual quality. The proposed algorithm has also been validated across different imaging depths with experiments conducted in both shallow and deep tissue. The above AR to OR domain transfer learning with GAN (AODTL-GAN) framework has enabled the enhancement target with limited amount of matched in vivo AR-OR imaging data.

With the rapid development of the internet of things (IoT), industry 4.0, smart manufacturing, intelligent building techniques, robots are becoming more and more demanding for emerging new applications. For robots used in complex environments, precise sensing of its surroundings is essential to enable safe and robust operation. Comprehensive and cognitive perception capability is needed to recognize human subjects in a complex and dynamic environment to avoid the possible collisions. Moreover, comprehensive sensing is required to enable accurate simultaneous localization and mapping (SLAM) under scenarios with clutters and moving human subjects. To achieve the goal, a CMOS-integrated radarassisted robot sensing platform is proposed. By leveraging the phased-array radar techniques and time-phase processing techniques, high accuracy can be achieved for localization and recognition of human subjects. Fabricated in a 65-nm CMOS process, the chip-scale radar sensing platform is with compact size. A series of experiments have been carried out on verifying the capabilities of the radar platform for ranging and human recognition based on vital signs, exploring the potential for seamless human-robot interaction applications.

A 1GHz configurable chirp modulation (CM) direct digital frequency synthesizer (DDFS) is presented and implemented in 65nm CMOS technology. This DDFS is designed to generate 70-86MHz chirp signal for X-band frequency modulated continuous wave (FMCW) radar system. The proposed design is composed of 64-bit frequency control word (FCW) serial peripheral interface bus (SPI) supported 20-bit frequency/phase accumulator and 10-bit linear/non-linear hybrid digital-to-analog convertor (DAC). This DDFS supports saw-tooth chirp mode and exhibits 20-900 μs time of chirp duration (TCD) and 1ms pulse recurrence frequency (PRF), dissipates 24mW@1GHz clock from a 1.2V supply. The DDFS core occupies 180μm×170μm area.

An ultra-lower power (ULP) MEMS-based FSK transmitter is implemented in 65 nm CMOS. The transmitter operates in ISM-915 MHz band using a binary FSK modulator employing the high-Q dual microelectromechanical system (MEMS) resonators. The transmitter using an adaptive fast switching binary FSK modulator generates FSK signals in 915 MHz band with -8.2 dBm output power, supporting up to 10 Mb/s data rate. The phase noise (PN) of the FSK modulator was measured for each of the two different operation frequencies, achieving -139.4dBc/Hz and -138.7dBc/Hz at a 1-MHz offset at 911.9 MHz and 923.1 MHz, respectively. At 10 Mb/s, the transmitter consumes 753 pW, which translates to energy-efficiency of 75.3 pJ/b.

Photoacoustic Microscopy (PAM) optical resolution (OR) imaging method is suited to get high resolution bio-tissue image but suffers from shallow penetration depth. By contrast, photoacoustic acoustic resolution (AR) imaging has deeper penetration depth but with degraded imaging resolution. Inspired by the current advances in the field of deep neural network (DNN), we proposed a new DNN framework named Prior Residual U-Net (PRU-Net), which combines U-Net with global residual block and image prior for AR image to OR image resolution enhancement. It helps to aggregate the advantages of both imaging methods without the cost of building extra physical setup. By training the model with experimentally obtained OR image and simulated AR image pairs, the model is able to enhance the image quality from AR image towards OR image to a huge extent. The enhancement results of sub-images and complete image have both validated this method's effectiveness qualitatively and quantitatively.

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging (DWA) digital circuits in the original MES method obsolete. Therefore, the complexity of the architecture is highly reduced, and the area is significantly reduced to 0.037 mm2. In addition, the power consumption for the MES implementation is significantly decreased by more than 7.3%. The proposed SAR ADC is fabricated in GF 40-nm CMOS technology. The measurements show that the proposed MES technique improves the SFDR from 64 to 102 dB and decreases the THD from -63.6 to -95.7 dB. The SNR and SNDR in a 20-kHz bandwidth are 91.6 and 90.2 dB, respectively. The power consumption is 383.4 μW with a 1.1-V power supply at a 16-MS/s sampling rate.

For wearable biomedical devices, it is essential to detect target signals under high noise and strong interferences. Moreover, it is critical to realize the system with compact size and easy implementation. To address both goals, this paper presents a chip-based photoacoustic (PA) sensor called QuACL. By leveraging the adaptive coherent lock-in technique, the high sensitivity and specificity can be achieved for detecting target signals. In-phase and quadrature PA templates are specifically designed based on the profile of the target signal and are generated by the FPGA board and the DAC board. The received signal is correlated with the templates to capture, track, and recover the target PA signal. Fabricated in 65-nm CMOS technology, the chip-based sensor system occupies only 0.6 mm2area. The robustness and versatility of the QuACL sensor system are verified by the experiments on discerning and recovering weak PA signals accurately.

Acoustic-resolution microscopy is an important imaging method in studying biological tissues with deep penetration. Using high-frequency transducer could reduce the size of the acoustic focal spot, thereby improving the resolution of microscopy. However, high-frequency photoacoustic signals usually suffer from acoustic attenuation which weakens their energy and distorts the image. In this paper, an attenuation compensation for high-frequency acoustic-resolution photoacoustic imaging is proposed. This technique upgrades the wavenumber term by considering acoustic attenuation and dispersion during wavefield extrapolation, which is a Fourier-domain image reconstruction. It is able to deal with the space-variant attenuation effect and inherits the high computational efficiency of wavefield extrapolation methods. According to the results of simulations and experiments, attenuation compensation successfully eliminates the dispersion induced reconstruction errors, obviously improves the resolution of the image and clearly presents the edges of targets.

High current, small area, and superior transient response LDO is gaining increasing attention for the battery-powered 5G mobile application. This paper presents an NMOS LDO realized in 0.13μm CMOS process featuring a 10mV undershoot and overshoot with 1A/100ns load current. The superior transient performance is achieved by a new multi-loop feedback scheme. The presented LDO also embodies a new frequency compensation scheme, which enables a stable 60dB dc loop gain despite 1A load current variation. This contributes to a small load regulation and line regulation of 0.6μV/A and 0.23mV/V, respectively. The LDO consumes 35μA quiescent current in mission mode. The silicon size of the LDO is 325μm × 106μm.

Flexible and wearable devices are emerging with the developing of the sensors and IoT (internet of the things). The power consumption and volume of such devices are dominant limitations for wearable feature in various applications. To meet the requirements, a photoacoustic receiver system-on-chip (SoC) is developed and fabricated with a novel correlation detection technique based on the early-and-late tracking. Through this method, output SNR of the receiver can be significantly improved. For this, a low power and high sensitivity analog front-end (AFE) with a noise shaping (NS) SAR ADC is implemented. As oversampling is necessary for the accurate delay of digital processing, noise shaping technique is implemented in the SAR ADC. Simulation results show that, the AFE achieves 70 dB dynamic range and 20 μV sensitivity for about 30 dB output SNR. The SAR ADC can obtain 71 dB SNDR under 50MSps sampling rate with the aid of the NS technique. Based on the analog circuits design, the digital part for the detecting technique is also implemented on chip. The whole power consumption is about 15 mW on the TSMC 65 nm CMOS process.

Photoacoustic imaging (PAI) is susceptible to speed of sound (SOS) differences in heterogeneous media which greatly reduce the resolutions and qualities of the imaging results. Several reconstruction methods have been reported to adapt for heterogenous media, but they are limited by specific deficiencies such as efficiency, accuracy, and model limitation problems. Among them, the plane wave model based on wavefield reconstruction is the most efficient and promising one for high-efficiency three-dimensional PAI. However, the classic plane wave model only suits for planar layered media, severely limiting its applications in practice. To this end, we modify the plane wave model to apply for irregularly layered heterogeneous media and propose a corresponding wavefield extrapolation to reconstruct photoacoustic image. This method employs split-step Fourier to compensate the SOS differences, extrapolates wavefields and reconstructs the image depth by depth. Furthermore, a floating discretization strategy is introduced to control and balance the efficiency and accuracy with a hyperparameter. The simulation and experiment results demonstrate that the proposed method can reconstruct the image with an equivalent resolution to time reversal's and even have higher efficiency and robustness. To reconstruct a three-dimensional image with 50×50×600 pixels, the proposed method takes only 5.5 seconds using a laptop loaded with Intel(R) Core (TM) i7-8550U CPU @1.8GHz.

Photoacoustic endoscopy (PAE), combining both advantages of optical contrast and acoustic resolution, can visualize the chemical-specific optical information of tissues inside human-body. Recently, its corresponding reconstruction methods have been extensively researched. However, most of them are limited on cylindrical scan trajectories, rather than a helical scan which is more clinically practical. On this note, this article proposes a methodology of imaging reconstruction and evaluation for helical scan guided PAE. Different from traditional reconstruction method, synthetic aperture focusing technique (SAFT), our method reconstructs image using wavefield extrapolation which significantly improves computational efficiency and even takes only 0.25 seconds for 3-D reconstructions. In addition, the proposed evaluation methodology can estimate the resolutions and deviations of reconstructed images in advance, and then can be used to optimize the PAE scan parameters. Groups of simulations as well as ex-vivo experiments with different scan parameters are provided to fully demonstrate the performance of the proposed techniques. The quantitatively measured angular resolutions and deviations agree well with our theoretical derivation results ${D}{\sqrt {r_{s}^{2} + \overline {h}^{{2}}} } / {[{1.25}({r}_{s} {r}_{d} + \overline {h}^{{2}})] }$ (rad) and $- \overline {h} {l} / ({r}_{s} {r}_{d} + \overline {h}^{{2}})$ (rad), respectively ${D},{r}_{d},\;{r}_{s},\overline {h} $ and ${l}$ represent transducer diameter, radius of scan trajectory, radius of source position, unit helical pitch and the distance from targets to helical scan plane, respectively). This theoretical result also suits for circular and cylindrical scan in case of $\overline {h} = {0}$ .

In this article, a dual loop-compensated, fasttransient, low-dropout regulator (LDO) is proposed for batterypowered applications. It is successfully implemented in a 0.18-μm CMOS process with a total silicon area of 210 μm × 593 μm. The proposed LDO is composed of two feedback loops. The fast feedback loop (FFL) employs direct output voltage spike detection through capacitive coupling, resulting in significantly improved, large signal transient response and loop bandwidth at the same time. Its voltage spike is 15 mV for a load step of 600 mA. The proposed LDO has a loop bandwidth of 2.3 MHz at a load current of 600 mA with a 30-μA no-load bias current. A power transistor with pseudo-equivalent series resistance (ESR) technique is proposed for loop stability improvement. It enables the usage of the low-cost, multilayer ceramic capacitors in mobile applications. The constant biased voltage feedback loop (VFL) has a loop gain larger than 60 dB under all load conditions, which enables a good line and load regulation.

The paper presents a two-stage cascade push-pull power amplifier (PA) with floating-body transistors in 130 nm Silicon-On-Insulator (SOI) CMOS process for IEEE 802.11ac application. In the proposed design, on chip baluns, which can realize impedance matching, are used in driver stage amplifier input and power stage amplifier output matching networks. The proposed PA can achieve high gain, high output power and wide bandwidth at the same time with 0.819mm2chip area including pads. With 2.5 V supply voltage, the implemented PA achieves 20.31 dB power gain with 3 dB bandwidth range from 3.9 GHz to 6.19 GHz, 20.96 dBm output power at 1 dB compression point (OP-1dB) and 9.85% power added efficiency (PAE).

A photoacoustic signal is proportional to a product of optical absorption coefficient and local light fluence; quantitative photoacoustic measurements of the optical absorption coefficients therefore require an accurate compensation of optical fluence variations. Usually, a supplementary diffuse optical tomography (DOT) is required to compensate the light fluence variations, but it is troubled by the bulky measurement system. In this paper, we propose a miniaturized dual-modality photoacoustic fusion imaging system. It utilizes an ultrasound sensor to receive photoacoustic signals for common photoacoustic imaging and extracts the passive ultrasound (PU) waves, backscattered laser-induced ultrasound waves, from the photoacoustic waves for diffuse reflectance (DR) imaging, simultaneously. Based on the dual-modality images of photoacoustic and DR, a further fusion photoacoustic imaging is implemented with the compensation the optical fluence variations. According to the experimental results, this miniaturized system can greatly reduce nearly 70% errors caused by the light fluence variations.

Diabetes mellitus is a prevalent metabolic disease which requires daily glucose monitoring for patients. Commercially available devices are all finger-prick which is painful and costly. Herein, we developed a portable and noninvasive glucose sensor based on photoacoustic (PA) technique. The size of the sensor main body is 17cm(L) × 14cm(W) × 10cm(H) with a weight of 650g (including a power bank). The system configuration is shown and the performance was evaluated by in vitro experiment on aqueous glucose solution at both high (1~8g/dL) and low concentrations (50~350 mg/dL). The R2and RMSE values achieved are 0.9526, 0.5903g/dL and 0.8966, 40.18mg/dL, respectively. Moreover, Clarke Error Grid analysis is also applied for physiological concentration prediction evaluation and 71.43% of data points fall in region A and the remaining points are in B, indicating the potential of our portable PA glucose sensor for clinical application.

A novel coil-based electromagnetic-induced thermo-acoustic system is presented for detecting the flaws inside a rail. The fundamental is derived and the overall energy density distribution is simulated using finite element method. This paper gives an overview of the system architecture and describes the design process in detail. A mixed numerical experimental methodology is employed to extract the lumped parameters of a planar coil with the ferrite plate for designing the matching network, and then the coil and rail are co-simulated to observe the current density distributions and directions. Through the relationship of energy density and depth in the rail, it is found that the thermal energy mainly concentrates at the surface local area. From the interaction between the coil and rail, the inductive power transfer topology is illustrated and the simplified equivalent circuit model is further obtained. By analyzing the simulated and measured data, the changes in the resistance and inductance are shown with the frequency increasing. The induced ultrasonic wave propagation is simulated inside the rail with flaws, where the wavefronts and reflected signals are observed. Finally, the experimental results demonstrate that the proposed design is feasible and a crack with a diameter of 8 mm can be detected in the rail.

Recently, many reconstruction methods have been developed to improve the lateral resolution of acoustic-resolution photoacoustic microscopy (ARPAM) in out-of-focus regions. Though these methods enhance image resolution to some extent, they require advanced computational hardware and large computational time, especially for three-dimensional (3-D) cases. However, some methods do not consider the finite size of a transducer, while others employ numerical discretization to build a focused transducer model that is less efficient and accurate. To overcome these problems, we propose a 3-D ARPAM imaging reconstruction method with high precision, high efficiency, and low memory cost. It inherits the framework of model-based reconstructions and incorporates the forward acoustic model in the hybrid domain. This hybrid-domain acoustic model promotes an analytical solution to establish a focused transducer model. Furthermore, the non-uniform fast Fourier transform (NUFFT) and deconvolution methods are introduced to reduce the required computational time and memory volume for 3-D reconstructions. According to the experimental results reconstructed by the proposed method, the lateral resolution of an ARPAM image recorded by a 20-MHz focused transducer (NA 0.393) can reach 88.39 [Formula: see text]. This resolution exceeds the diffraction limitation of the focused transducer ( [Formula: see text]). When reconstructing a 3-D image with 200×200×150 pixels, the proposed method takes only 8.15 s using a laptop loaded with Intel Core i7-8550U CPU at 1.8 GHz and 1.06-GB memory.

A handheld approach to 3D photoacoustic imaging is essential in clinical applications. To this end, we develop a 3D handheld photoacoustic imager for dynamic (temporally and spatially) volumetric visualization. In this 3D imager, the optically transmitting part and the acoustically receiving part are integrated into a single handheld probe with a compact size about 160 mm ×64 mm ×40 mm. Besides, a dedicated imaging reconstruction algorithm for the heterogeneous medium is developed based on the phase-shift migration method in the frequency domain, which deals well with the stratified condition in the designed system. Dynamic 3D imaging supporting flexible handheld operation is demonstrated with needle biopsy and in vitro temperature measurement for photothermal therapy. The development of such a 3D handheld photoacoustic system paves the way for compact and handheld-operating implementations, and its further clinical exploration is promising.

Multi-layer light field displays are a type of computational three-dimensional (3D) display which has recently gained increasing interest for its holographic-like effect and natural compatibility with 2D displays. However, the major shortcoming, depth limitation, still cannot be overcome in the traditional light field modeling and reconstruction based on multi-layer liquid crystal displays (LCDs). Considering this disadvantage, our paper incorporates a salience guided depth optimization over a limited display range to calibrate the displayed depth and present the maximum area of salience region for multi-layer light field display. Different from previously reported cascaded light field displays that use the fixed initialization plane as the depth center of display content, our method automatically calibrates the depth initialization based on the salience results derived from the proposed contrast enhanced salience detection method. Experiments demonstrate that the proposed method provides a promising advantage in visual perception for the compressive light field displays from both software simulation and prototype demonstration.

Integrated frequency modulated continuous wave (FMCW) radar on chip (RoC) shows huge potential on real-time, versatile, wireless monitoring of human health conditions with low power, high sensitivity and compact size. This paper presents a Ku-band FMCW RoC working at 15 GHz center frequency, which can realize accurate continuous health monitoring based on interferometry phase analysis algorithm. A digital-tunable mixed-signal-mode FMCW chirp synthesizer is designed to ensure the phase accuracy with high power efficiency. A saturated driver-amplifier and power-amplifier chain is used to suppress the chirp ripples, thus ensuring the accurate phase measurement. Fabricated in 65 nm CMOS technology, the prototype demonstrates 1 GHz chirp bandwidth with 1.2 V supply and 238 mW power consumption, which satisfies the low-power requirement for continuous-time healthcare monitoring applications. Experiments on detecting various kinds of micro physiological signals are carried out using the FMCW radar chip prototype based on the phase analysis algorithm. The radar and the phase analysis algorithm can be further integrated into an ASIC to realize higher performance on healthcare monitoring.

A miniaturized sensing system for noninvasive measurement of blood temperature with relatively deeper penetration has being long pursued with limited success. Here, we develop a novel photoacoustics based portable sensor for noninvasive monitoring of blood temperature with high accuracy, deep penetration depth and real time capability. Optical module (laser diode with collimation lens) and acoustic module (ring ultrasound transducer with an optical/acoustic transparent Polydimethylsiloxane coupling layer) of the system is integrated to a compact sensor head with a size similar to a human thumb. Main body is battery-powered to provide the laser driver, data acquisition and also signal processing. The overall system size is around 14 cm×8 cm×3 cm. Temperature calibration and measurement is demonstrated both on phantom and animal to achieve a high accuracy of 0.2 and 0.5 degree respectively, with a fast refreshing speed of 80 Hz. In the future, such developed photoacoustic temperature sensing device can potentially become a wearable patch sensor with further miniaturization of laser diode and use of MEMS-based piezoelectric micro-machined ultrasonic transducers (PMUT).

In this paper, a delay locked loop (DLL) based configurable multi-phase clock generator with wide operating range and high resolution is proposed. It is implemented by adopting array of configurable DLLs and is able to generate multi-phase frequencies with true-time-delay, which is essential in a wideband FMCW phased array system. Fabricated in a 40nm CMOS process, the proposed multi-phase clock generator achieves configurable phase delay with high resolution of 7ps under varies of reference frequency from 400MHz to 2.5 GHz. The clock generator consumes 20.9mW from a 1.1V supply.

The paper presents a wideband, low-power chirp synthesizer for Ku-band FMCW radars. The DDS-driven ADPLL chirp synthesizer generates chirps up to 2GHz bandwidth. A low-power DDS is employed to generate a stepped reference frequency for ADPLL to ensure the long term chirp linearity, while the ADPLL fulfill the ramp-interpolating linearization by generating a narrow band chirp within the step frequency. The entire chirp benefits from the phase domain modulation and mitigates ADPLL loop bandwidth variation to achieve high linearity and low power. A novel adaptive ramping control scheme is adopted to ensure the chirp rate is constant after combining the narrow band chirp segments. By this two-stage chirp generation, a 2-GHz chirp is achieved with low relative frequency RMS error. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.9GHz to 15.9GHz with configurable rate from 0.25 to 4GHz/ms, and consumes 53.8mW.

A novel noninvasive microwave biosensor for glucose measurement was designed, developed and tested to show its potential for real-time and continuous glucose monitoring. The reflected S-parameter S11 was investigated with different glucose concentrations within the range of 0.5 ~ 7 g/dL. The magnitude and resonance frequency information were utilized for prediction and then combined by data fusion to enhance the accuracy. The prediction results by magnitude and resonance frequency of S11 versus reference glucose concentration show root-mean-squared errors (RMSE) of 0.2887 g/dL and 0.1681 g/dL respectively. The prediction by data fusion shows RMSE value of 0.1364 g/dL indicating significant accuracy improvement of 52.75% and 18.86% compared to single parameter based magnitude and frequency predictions.

This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around -52 to -55 dB at Nyquist input. Then, a tap-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Also, a full analysis of the effects of the various parameters on the time skew generated spur levels is presented, which indicates that the time skew error level is related to the length of calibration filters, calibration range, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a low-cost high-speed subradix-2 searching technique. The reference interference of nonbinary TI ADCs is discussed and tolerated by the subradix-2 searching scheme. The proposed adders-based encoding circuit is optimized with lower propagation delay to meet high-speed requirements. The prototype was fabricated in a 65-nm CMOS technology. The measurement results show that the ADC achieves a signal-to-noise-plus-distortion ratio of 49.6 dB with a power of 15.95 mW and a figure of merit of 63 fJ/conversion step when operating at 1-GS/s and 458.1-MHz Nyquist input. The ADC core achieves an area of 0.158 mm2.

Light field images can be conveniently captured by consumer-level plenoptic cameras. However, as the resulting data rates are very high, providing efficient compression for this type of data is of critical importance. This remains an open problem which has recently attracted a lot of attention from the coding community. State-of-the-art compression systems prove to be inefficient when directly applied on this type of data due to the inherent spatial discontinuities in light field images. In this paper, a novel intra-prediction method for disk-shaped pixel clusters is proposed. An L1 minimization of the prediction residuals is performed followed by clustering of the predictors, leading to an optimized set of predictors for the macro-pixels. Furthermore, directional intra-prediction modes based on HEVC are devised for the macro-pixels. Experimental results obtained on the EPFL light field image dataset demonstrate that the proposed coding scheme yields an average of 3.22 dB and 1.45 dB gain in PSNR, and 59.6% and 30.88% average rate savings compared to HEVC and the state-of-the-art in light field image coding respectively.

A Ku-band wideband power amplifier (PA) for FMCW radar application is proposed and implemented in 65-nm bulk CMOS technology. The PA consists of 3 stages of class AB amplifiers to achieve high gain and high power efficiency. To obtain low group delay (GD), low amplitude ripple and wide bandwidth, transformer and inductor based matching network is designed to meet the requirements. Including pads, the PA occupies a compact chip area of 0.62 mm2. Consuming 118 mA current from 1.2 V supply voltage, it demonstrates output saturation power of 13.04 dBm. The measured 3 dB bandwidth is 5.5 GHz with maximum gain 20.65 dB at 15.5 GHz. Finally, the PA is integrated with a (frequency modulated continuous wave) FMCW signal generator to constitute a FMCW radar transmitter.

A high gain decibel (dB)-linear programmable gain amplifier (PGA) for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed PGA employs binary-weighted switching array as pseudo-exponential function to achieve large dynamic range. A current compensation circuit is proposed in fine gain step cell to decrease gain step error. This PGA has been implemented in 65 nm CMOS technology embed ding in a SAR receiver. Measurement results show that the proposed PGA exhibits a dB-linear gain range of 60 dB from 10.47 to 69.63 dB with a gain error of less than ±0.39 dB, a input 1-dB compression point (IP-1dB) of -67.8 to -18.4 dBm, a 3-dB bandwidth of 0.8 to 50 MHz at the maximum gain while consuming less than 5.4 mA from a 1.2 V supply.

This live demonstration presents a first-in-kind fully integrated Ku-band Synthetic Aperture Radar (SAR) transceiver chip in 65-nm CMOS that fits for micro-UAVs. The transmitter presents 13.3-dBm output power and 1.48 GHz chirp bandwidth centering at 15 GHz. The receiver front-end attains 23.5-dB gain, -33-dBm IPldB and 5.6-to-6.3dB noise figure. The receiver analog baseband achieves 0.68-to-9.8-MHz programmable passband and 55-dB variable gain range. The integrated ADC has 9.4-bit ENOB. The SAR chip achieves super-resolution of 11.2 cm and consumes only 260-mW power. The ranging and imaging functions of the prototype are showcased.

The advent of consumer-level plenoptic cameras has sparkled the interest towards the design of efficient compression techniques for light field images. State-of-the-art compression systems such as HEVC prove to be inefficient when directly applied on this type of data due to the inherent spatial discontinuities among neighboring microlens images. In this paper, a novel light field image compression system is proposed. The disk-shaped pixel clusters corresponding to each microlens in the light field image are efficiently predicted based on the neighboring disks. In this context, an optimized linear prediction design based on L1 minimization of the residuals is proposed. K-means clustering is employed on training data in order to determine the optimized set of predictors. The experimental results on an extensive set of light field images demonstrate that the proposed coding scheme yields an average of 2.93 dB and 3.22 dB gain in PSNR, and 52.67% and 57.27% average rate savings compared to HEVC and JPEG2000 respectively.

This paper describes time-to-digital converter (TDC) architecture capable of achieving subgate-delay resolution and large detection range at the same time with low power consumption. The proposed TDC is based on a parallel sampling ring oscillator with power gating and dynamic element matching (DEM). Through digital background calibration, the time resolution is determined by the delay difference between successive sampling clocks instead of buffer delay. The ring oscillator is enabled only during the incoming time pulsewidth, leading to low power consumption. A new buffer circuit implementation which enables the ring oscillator to settle to a known position after the ring oscillator stops is proposed. Furthermore, the stop position is latched by cross-coupled inverters to achieve immunity to leakage issues. For each incoming time pulse, the ring oscillator starts oscillation from the buffer before which the previous conversion stops, and thus, it also achieves barrel-shift algorithm for DEM and mitigates buffer mismatch impact. The design is fabricated in 65-nm CMOS technology and occupies a 0.4 mm × 0.3 mm chip area. Measurements of the prototype IC demonstrate a detection range of 98 ns with 6 ps/LSB. It consumes 280 μW from a 1.2 V power supply when operating at a 1-MS/s sampling rate. The measured integral nonlinearity and differential nonlinearity are 0.5 and 0.1 LSB, respectively. Measurements of the prototype IC also demonstrate a single-shot precision of less than 11 ps.

This brief presents a low-computational, flexible nonbinary searching technique for high-speed successive approximation register (SAR) analog-to-digital converters (ADCs). By embedding the redundant weights into each capacitor branch of digital-to-analog converter (DAC) array, the conventional binary DAC array is customized as a nonbinary DAC array without additional control logics, resulting in fast conversion and negligible overhead. The weight of each branch could be defined flexibly with certain constraints, which is derived in this brief. Moreover, the nonbinary output codes are encoded to binary codes by adder-based encoding logics that show far less power and area penalty. To demonstrate the proposed nonbinary searching technique, a 10-bit 280-MS/s high-speed SAR-ADC is presented, which achieved an signal-to-noise-distortion ratio of 52.4 dB and a figure of merit of 21 fJ/conversion step.

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, +0.005/fs].

In this paper, we propose a method to optimize two-layer light field display using depth initialization. In contrast to existing trade-off work between performance and processing time, this paper firstly models the display principle of layered light field display, and then performs layered initialization with the prior known depth of 3D objects, and finally optimizes the layered images for light field display. Experiments demonstrate that the proposed initialization method can obviously save the iterations and related processing time for the existing online or offline algorithms to achieve the same reconstructed peak signal to noise ratio (PSNR) and present a better subjective reconstructed performance using the same computation resource.

A 95 dB dynamic range automatic gain control (AGC) circuits and systems for Multi-standard Digital TV (DTV) tuner has been presented. A novel automatic gain control method composed of RFAGC and IFAGC is proposed with improved SNR. A wideband single-ended LNA based on current-reuse technique with low temperature variation is proposed. The complete AGC circuits are fabricated in six-metal 0.18-μm CMOS technology and consume DC current of 32.5 mA from a 1.8 V supply. The RF front-end circuit achieves 90 dB maximum gain, 95 dB gain control range, a 4 dB noise figure and an IIP3 higher than -28 dBm at the maximum gain.

In this paper, a statistic based time skew calibration method for time-interleaved ADCs is presented. By comparing the mean value of the multiplication of signals in two adjacent channels, the time skew can be estimated. Subsequently, a capacitor array based digitally controlled delay block placed in sampling clock path is adopted to compensate the time skew. In addition, the precision of calibration is further improved through using a monotonic small capacitor array. In a 4-channel 1GS/s 12-bit TI-ADC system, the spurious free dynamic range (SFDR) can be improved to 77.5dB with 0.25ps LSB in the digitally controlled delay block.

The paper presents a design of a low power wide output bandwidth FMCW frequency synthesizer for radar applications. The proposed FMCW frequency synthesizer adopts digital phase locked loop approach and has been implemented in 65 nm CMOS technology. A phase domain model is proposed for analyzing the digital phase locked loop architecture. The FMCW synthesizer is able to generate triangularly modulated continuous wave of 3GHz output bandwidth in X band with linearity error less than 1.4×10-4. It consumes only 7 mA under 1.2 V power supply. The measured phase noise is -105dBc/Hz at 1MHz offset with a centre frequency of 10 GHz.

This paper proposes a frequency-interleaved ADC (FI-ADC) architecture, which can avoid time skew problem existing in time-interleaved ADC (TI-ADC). The analysis filter bank of the FI-ADC is implemented by low order analog filters and can be integrated easily. In addition, prototype of an 8-channel 2GS/s 12-bit FI-ADC is designed. Based on the spurious-free dynamic range (SFDR), the comparison of variation of analog filter coefficients in FI-ADC and time skew in TI-ADC is done. Simulation results show that FI-ADC is more suitable for GHz implementation, and the proposed FI-ADC has a better gain mismatch tolerance than TI-ADC.

Spectrum sensing in cognitive radio is an important part to detect unknown signal(s). This paper introduces a spread spectrum technique for spectrum sensing in cognitive radio in order to detect the availability of input spectrum within 800MHz to 3.5GHz frequency band. The designed receiver front-end IC can achieve the simulated gain of 30dB, QVCO phase noise of -117dBc/Hz at 1MHz offset at 2.4GHz carrier, noise figure of 5.3dB, IIP3of -21dBm and total power dissipation of 90mW, including VCO and Mixer buffer.

This paper presents a fully integrated 2-channel beamformer for 3-5 GHz impulse-based ultra-wideband (IR-UWB) receiver. A true time delay (TTD) element with optimized cutoff frequency and active loss compensation is proposed to provide large continuous time delay tuning with reduced chip size and power consumption. Each beamforming channel has a measured peak gain of 18.5 dB and a continuous time delay between 0-255 ps. The proposed beamformer can provide maximum scan angle of up to ±60° for two antennas with 8 cm spacing. The whole beamformer consumes 38 mA from a 1.8V DC power supply.

This paper investigates the efficient design of the PHY layer architecture for wireless body area networks (WBAN), which targets on ultra-low power consumption with reliable quality of service (QoS). A low cost baseband transceiver specification and a data processing flow are proposed with a comparatively low-complexity control state machine. A multifunctional digital timing synchronization scheme is also proposed, which can achieve packet synchronization and data recovery. The proposed baseband transceiver is fabricated in an 0.18- μm CMOS process. With a 1.1 V supply and 4 MHz system clock, this baseband chip only consumes 34 μW in transmitter (TX) mode and 39.6 μW in receiver (RX) mode. To demonstrate and to optimize the reliability of the proposed design, the dedicated bit-error-rate and packet-error-rate analysis is reported.

This paper proposes a power and area efficient electrocardiogram (ECG) signal processing application specific integrated circuits (ASIC) for wireless body area networks (WBAN). This signal processing ASIC can accurately detect the QRS peak with high frequency noise suppression. The proposed ECG signal processor is implemented in 0.18μm CMOS technology. It occupies only 1.2 mm2in area and 9μW in power consumption. Therefore, this ECG processor is convenient for long-term monitoring of cardio-vascular condition of patients, and is very suitable for on-body WBAN applications.

The motivation for asynchronous logic at this juncture of CMOS technology is the issues of power density, process variation and integration limit, where synchronous logic is facing a myriad of problems. Asynchronous templates are the fundamental building blocks of asynchronous circuits and systems, and together with asynchronous EDA tools enable the design of complex systems at a high level of abstraction (similar to the RTL-to-GDSII flow in synchronous design). However, akin to the impact of library cells to the overall system performance in the conventional synchronous flow, the diverse availability of asynchronous template libraries requires prudent contemplation. Therefore in this paper, the most eminent matched-delay asynchronous template families reported to date will be presented, and followed by an in-depth comparison of various design figure of merits (FOMs) - template area, static/dynamic capacity, cycle time, latency, throughput and Et2. The most aggressive template (GasP) can reach a maximum throughput of 5 Giga items/s on 0.13 mum @ 1.2 V.

In this paper, we propose a methodology for interfacing synchronous IP memory blocks (read-only memory (ROM) and random-access memory (RAM)) with asynchronous-logic digital systems based on dual-rail, 4-phase signaling. The memory blocks (ROM and RAM) of an instruction-set compatible 8051 microcontroller (A8051) is implemented with Artisan IP memory blocks for the IBM 0.13μm CMOS technology. Interface circuits play the role of (1) synchronizing all the asynchronous input channels driving the IP memory blocks, (2) single rail signaling logic to dual-rail 4-phase signaling logic conversion and vice versa, and (3) capturing synchronous signals in memory read cycles and driving asynchronous channels. The A8051 with the proposed ROM and RAM design operates at 28% higher MIPS rate (millions of instructions per second), dissipates 20% lower energy per instruction, ∼50% lower Et2and occupies 19% lesser area, as compared to the A8051 with register-based memory.

A novel multi-band low noise amplifier (LNA) that allows simultaneous reception of signals from several wireless standards is designed and implemented using a 0.18-μm CMOS technology. The circuit topology consists of a 3-stage wideband LNA and 2 notch filters. The designed LNA can provide concurrent three bands over 0.935~5.825 GHz with measured gain (S21) of 15~24 dB, input reflection ratio (S11) of -35~-7 dB, noise figure (NF) of 4.4~4.78 dB, and 3rdorder input intercept point (IIP3) of -15.3~-12.4dBm respectively. In addition, a minimum 8 dB of inter-band gain suppression is achieved. This work has achieved a better figure of merit (FOM) than other related works, in terms of gain, noise figure and power consumption trade-offs.

In this paper, we describe an asynchronous (async) dual-rail 13×13-bit multiplier based on the single-track full-buffer (STFB) template. We propose several techniques to improve the energy-efficiency of the template. Firstly, we propose a new output driver sub-cell for the template suitable for driving smaller loads with higher energy efficiency. Secondly, we propose non-handshaking channels in order to reduce the pipeline stages in our design to trade-off throughput for higher energy-efficiency and smaller area. Lastly we propose using non weak-condition AND, 3-to-2 and 2-to-2 compressor cells to achieve lower forward latency. The performance of the proposed multiplier design is simulated using the TSMC 0.18μm library at the transistor level. The proposed design is 15% more energy-efficient, has 14% lower latency and 34% smaller as compared to the same implementation using the STFB template.

A synchronization scheme for impulse radio (IR) UWB receiver based on Trigg and Leach detector was proposed in this paper. The analysis revealed that additional gain of 5dB ~ 10dB was achieved with the proposed scheme. For example, to achieve the specifications of detection probability Pdges 0.8 and false alarm probability Pfales 10-6, the conventional matched filter (MF) based scheme requires SNR of 15dB, while only 5dB is needed for the proposed scheme. The performance of the proposed scheme was further verified by simulations

In this paper, the problem of time-varying parametric autoregressive (AR) model identification by wavelets is discussed. Firstly, we derive multiresolution least squares (MLS) algorithm Gaussian time-varying AR model identification employing wavelet operator matrix representation. This method can optimally balance between the over-fitted solution and the poorly represented estimation. Utilizing multiresolution analysis techniques, the smooth trends and the rapidly changing components of time-varying AR model parameters can both be estimated accurately. Then, the proposed MLS algorithm is combined with the total least squares algorithm for noisy time-varying AR model identification. Simulation results verify the effectiveness of our algorithms.